C
Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
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Journal ArticleDOI
Substrate hole current and oxide breakdown
TL;DR: In this article, it was shown that hole generation mechanism is linked to oxide time-dependent breakdown and when the hole fluence reaches a certain critical value, breakdown occurs, in agreement with a hole-trapping-induced breakdown model.
Journal ArticleDOI
A capacitorless double-gate DRAM cell
C. Hu,Tsu-Jae King,Chenming Hu +2 more
TL;DR: In this article, a capacitorless double-gate DRAM (DG-DRAM) cell is proposed to reduce off-state leakage and disturb problems by using a thin, lightly doped body.
Journal ArticleDOI
A physical and scalable I-V model in BSIM3v3 for analog/digital circuit simulation
Yuhua Cheng,Min-Chie Jeng,Zhihong Liu,Jianhui Huang,Mansun Chan,Kai Chen,Ping Keung Ko,Chenming Hu +7 more
TL;DR: A new physical and continuous BSIM (Berkeley Short-Channel IGFET Model) I-V model in BSIM3v3 is presented for circuit simulation, which allows users to accurately describe the MOSFET characteristics over a wide range of channel lengths and widths for various technologies, and is attractive for statistical modeling.
Journal ArticleDOI
Impact of spatial intrachip gate length variability on the performance of high-speed digital circuits
TL;DR: A location-dependent timing analysis methodology that allows mitigation of the detrimental effects of Lgate variability and a tool linking the layout-dependent spatial information to circuit analysis are proposed, which allows estimating performance degradation for the given circuit and process parameters.
Proceedings ArticleDOI
Gate length scaling and threshold voltage control of double-gate MOSFETs
TL;DR: In this article, the scaling issues of double-gate MOSFETs are explored in the nanoscale regime and the advantages of using alternative channel materials to facilitate scaling are investigated.