C
Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
Bimodal electromigration mechanisms in dual-damascene Cu line/via on W
TL;DR: In this article, the authors investigated the distribution of failure lifetimes in 0.23 /spl mu/m wide Cu dual-damascene lines connected to W underlayers and determined that void growth at the vicinity of the cathode end of the line/via was the cause of line failure.
Proceedings ArticleDOI
First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf 0.5 Zr 0.5 O 2 Ferroelectric Gate Stack
Q. H. Luc,C. C. Fan-Chiang,S. H. Huynh,Po-Tsang Huang,H. B. Do,M. T. H. Ha,Y. D. Jin,T. A. Nguyen,K. Y. Zhang,H. C. Wang,Lin Yue-Cin,Yen-Han Lin,Chenming Hu,H. Iwai,Edward Yi Chang +14 more
TL;DR: In this paper, the negative capacitance (NC) In 0.53 Ga 0.47 As nMOSFET with 8-nm Hf 0.5 Zr 0.3 O 2 (HZO) dielectric for sub-60 mV/dec subthreshold swing (SS) was demonstrated.
Journal ArticleDOI
High-performance bipolar technology for improved ECL power delay
James D. Warnock,John D. Cressler,Keith A. Jenkins,C.L. Stanis,J.Y.-C. Sun,Denny D. Tang,E. Petrillo,Chenming Hu +7 more
TL;DR: In this article, a shallow trench process for isolation of bipolar devices is shown to allow butting of the emitter-base junction to the field oxide edge, thereby greatly reducing the overall device size and parasitic capacitances.
Journal ArticleDOI
Hot-carrier-induced degradation in p-MOSFETs under AC stress
TL;DR: In this paper, a quasistatic model using parameters extracted from DC stress data was used to calculate the lifetime of inverter-like waveforms under AC stress. But the model was not suitable for waveforms with turnoff transient occurring in the presence of high drain voltage.
Proceedings ArticleDOI
Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits
Chih-Chao Yang,Tung-Ying Hsieh,Po-Tsang Huang,Kuan-Neng Chen,Wan-Chi Wu,Shih-Wei Chen,Chia-He Chang,Chang-Hong Shen,Jia-Min Shieh,Chenming Hu,Meng-Chyi Wu,Wen-Kuan Yeh +11 more
TL;DR: In this paper, a location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO 2, which exhibit steep sub-threshold swing and high I on /I off (>106).