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Chenming Hu
Researcher at University of California, Berkeley
Publications - 1300
Citations - 60963
Chenming Hu is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: MOSFET & Gate oxide. The author has an hindex of 119, co-authored 1296 publications receiving 57264 citations. Previous affiliations of Chenming Hu include Motorola & National Chiao Tung University.
Papers
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Proceedings ArticleDOI
Statistical modeling of silicon dioxide reliability
TL;DR: In this paper, a technique is presented for predicting lifetime of an oxide to different voltages, different oxide areas and different temperatures, using the defect density model in which defects are modelled as effective oxide thinning, many reliability parameters such as yield, failure rate and screen time/screen yield can be predicted.
Journal ArticleDOI
A CV technique for measuring thin SOI film thickness
TL;DR: In this article, a technique is developed to measure silicon-on-insulator (SOI) silicon device film thickness using a MOSFET, based on CV measurements between gate and source/drain at two different back-gate voltages.
Proceedings ArticleDOI
Impact of gate-induced drain leakage current on the tail distribution of DRAM data retention time
K. Saino,S. Horiba,S. Uchiyama,Y. Takaishi,M. Takenaka,T. Uchida,Y. Takada,K. Koyama,H. Miyake,Chenming Hu +9 more
TL;DR: In this article, a new model for leakage mechanism in tail-mode bits of DRAM data retention characteristics was proposed, where the root cause is electric field enhancement caused by metal precipitates located at the gate-drain overlap region.
Patent
Novel CMOS device
TL;DR: In this paper, a method comprising providing a substrate having an NMOS device adjacent a PMOS device and forming a first stress layer over the NMOS and PMOS devices was proposed.
Journal ArticleDOI
Predicting CMOS speed with gate oxide and voltage scaling and interconnect loading effects
TL;DR: In this article, the optimal gate oxide thickness for different interconnect loading was analyzed at supply voltages of 1.5-3.3 V. I/sub dsat/ can be accurately predicted from a universal mobility model and a current model considering velocity saturation and parasitic series resistance.