There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

The electrostatic discharge (ESD) protection capability of SOI CMOS output buffers has been studied with Human Body Model (HBM) stresses. Experimental results show that the ESD voltage sustained by SOI CMOS buffers is only about half the voltage sustained by the bulk NMOS buffers. ESD discharge current in a SOI CMOS buffer is found to be absorbed by the NMOSFET alone. Also, SOI circuits display more serious reliability problem in handling negative ESD discharge current during bi-directional stresses. Most of the methods developed for bulk technology to improve ESD performance have minimal effects on SOI. A new Through Oxide Buffer ESD protection scheme is proposed as an alternative for SOI ESD protection. In order to improve ESD reliability, ESD protection circuitries can be fabricated on the SOI substrate instead of the top silicon thin film, after selectively etching through the buried oxide. This scheme also allows ESD protection strategies developed for bulk technology to be directly transferred to SOI substrate. >

ESD reliability and protection schemes in SOI CMOS output buffers

A gate electrode is formed including a gate conductor overlying a high dielectric constant (k) gate dielectric. A small or round substrate recess of controlled depth is formed around the gate electrode. This controlled substrate recess will improve current drive degradation performance of the device.

Devices with high-k gate dielectric

Scaling effects on Cu microstructure, resistivity, dielectric materials, and electromigration (EM) and time dependent dielectric break down (TDDB) reliabilities for Cu interconnects were reviewed. A simple empirical model of Cu resistivity related to Cu line area was presented. Cu line microstructures containing small grains mixed with large bamboo grains in Cu damascene lines from technology nodes below 65 nm were observed. As predicted in previous work, the EM lifetime was found to degrade by about 50% for every new generation even for the same current density. The Cu grain size was found to have a large impact on pure Cu and Cu alloy EM lifetime and activation energy Ea. Ea for pure Cu line capped with selective electroless CoWP on near-bamboo, bamboo-polycrystalline, to polycrystalline only line grain structures was reduced from 2.2 eV to 1.7 eV to 0.75 eV, respectively. Ea for 40 nm wide bamboo-polycrystalline lines capped with selective chemical vapor deposition (CVD) Co was found to be 1.7 eV. Using pure Cu and Cu(Al) or Cu(Mn) diluted impurity seed layers in 40 nm wide, bamboo-polycrystalline microstructure lines and above 100 nm wide, near bamboo-like grained lines, Cu-alloy lines enhanced EM lifetimes and increased QEM from 0.9 to 1. eV and 1.0 to 1.2 eV, respectively, compared to pure Cu lines. Inter-level TDDB testing on vias connecting M1 to M2 with a via chamfer angle that varied from 58o to 81o have very similar performance with intra-level M2 data with no vias tested at the same field. This result combined with the data from a separate study, which allowed the chamfer path to be isolated from the M2-level path, suggested that the failure took place preferentially along the weak cap/ILD interface at M2 and not at the via chamfer. TDDB acceleration data indicated that the root E model was overly conservative and a more aggressive model provided a better fit to the data. TDDB lifetimes correlated fairly well with the percentage of porosity in the dielectric materials.

Materials and scaling effects on on-chip interconnect reliability

AC effects in IC reliability

SOI MOSFETs are susceptible to the local thermal heating generated in the channel due to the lesser thermal conductivity of their buried oxide. Even with a /spl sim/100 nm thin buried oxide, SOI MOSFET DC I-V characteristics, from which SPICE parameters are extracted, show current loss due to the self-heating. On the other hand, for most logic circuits in an LSI, the self-heating effect is insignificant. Since the average power per device is low and the switching time (/spl sim/10 ps) is much shorter than the thermal constant (/spl sim/100 ns), the device temperature increase due to the self-heating is quite small. Therefore, for an accurate circuit design, we must correct the DC I-V data for the self-heating. In this paper, the thermal dissipation paths in SOI MOSFETs are investigated via experiments and modeling.

Chenming Hu

Papers

ESD reliability and protection schemes in SOI CMOS output buffers

Devices with high-k gate dielectric

Materials and scaling effects on on-chip interconnect reliability

AC effects in IC reliability

SOI MOSFET thermal conductance and its geometry dependence