There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

抗原变异可使得多种致病微生物易于逃避宿主免疫应答。表达在感染红细胞表面的恶性疟原虫红细胞表面蛋白1（PfPMP1）与感染红细胞、内皮细胞、树突状细胞以及胎盘的单个或多个受体作用，在黏附及免疫逃避中起关键的作用。每个单倍体基因组var基因家族编码约60种成员，通过启动转录不同的var基因变异体为抗原变异提供了分子基础。

疟原虫var基因转换速率变化导致抗原变异[英]／Paul H, Robert P, Christodoulou Z, et al//Proc Natl Acad Sci U S A

Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

/pdf/high-k-gate-dielectrics-current-status-and-materials-zjvba0c4u8.pdf

High-κ gate dielectrics: Current status and materials properties considerations

The CMOS technology area has quickly grown, calling for a new text--and here it is, covering the analysis and design of CMOS integrated circuits that practicing engineers need to master to succeed. Filled with many examples and chapter-ending problems, the book not only describes the thought process behind each circuit topology, but also considers the rationale behind each modification. The analysis and design techniques focus on CMOS circuits but also apply to other IC technologies.
Table of contents

1 Introduction to Analog Design
2 Basic MOS Device Physics
3 Single-Stage Amplifiers
4 Differential Amplifiers
5 Passive and Active Current Mirrors
6 Frequency Response of Amplifiers
7 Noise
8 Feedback
9 Operational Amplifiers
10 Stability and Frequency Compensation
11 Bandgap References
12 Introduction to Switched-Capacitor Circuits
13 Nonlinearity and Mismatch
14 Oscillators
15 Phase-Locked Loops
16 Short-Channel Effects and Device Models
17 CMOS Processing Technology
18 Layout and Packaging

/pdf/design-of-analog-cmos-integrated-circuits-35wxhwa3a6.pdf

Design of Analog CMOS Integrated Circuits

Nanocrystals (NCs) discussed in this Review are tiny crystals of metals, semiconductors, and magnetic material consisting of hundreds to a few thousand atoms each. Their size ranges from 2-3 to about 20 nm. What is special about this size regime that placed NCs among the hottest research topics of the last decades? The quantum mechanical coupling * To whom correspondence should be addressed. E-mail: dvtalapin@uchicago.edu. † The University of Chicago. ‡ Argonne National Lab. Chem. Rev. 2010, 110, 389–458 389

/pdf/prospects-of-colloidal-nanocrystals-for-electronic-and-3dxpyhl3r7.pdf

Prospects of Colloidal Nanocrystals for Electronic and Optoelectronic Applications

We model the effects of cross-sectional radius scaling on ${C}$ – ${V}$ and ${I}$ – ${V}$ characteristics of gate-all-around FETs (GAAFETs), capturing the continuous transition from a 3-D electron system to a 1-D electron system. We have obtained computationally efficient models for effective mass, bandgap, and subband energies as functions of the cross-sectional radius and gate voltage based on simple approximate analytic expressions. Together, they provide a compact model for VLSI circuit simulation, especially for analog and RF circuits that will be seriously affected by the new humps and peaks in ${C}$ – ${V}$ and ${I}$ – ${V}$ introduced by the subbands. The model has been validated with ${k}\cdot {p}$ -based technology computer aided design simulations as well as measured data. To the best of our knowledge, this is the first compact model capturing cross-sectional size-dependent dimensional crossover (3-D to 1-D) in ${I}$ – ${V}$ and ${C}$ – ${V}$ for GAAFETs.

Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition

In this paper, self-consistent three-dimensional (3D) device simulations for exact analysis of thermal transport in FinFETs are performed. We analyze the temperature rise in FinFET devices with the variation in the number of fins (N fin), shape of fins and fin pitch (F pitch). We investigate that the thermal resistance R th has nonlinear dependency on N fin and F pitch. We formulate a model for thermal resistance behavior correctly with N fin and F pitch variation. The proposed formulation is implemented in industry standard Berkeley short-channel independent gate FET model for common multi-gate transistors (BSIM-CMG) and validated with both experimental data and TCAD simulations.

https://iopscience.iop.org/article/10.7567/JJAP.55.04ED11/pdf

Modeling of nonlinear thermal resistance in FinFETs

/pdf/an-advanced-surface-potential-plus-mosfet-model-34yoy1ilpi.pdf

An advanced surface-potential-plus MOSFET model

A process for forming gate oxides of multiple thicknesses. In one embodiment (1A-C), oxygen (16) is implanted through a sacrificial oxide (12) into selected regions of a silicon substrate (10) according to a patterned photoresist mask (14). After stripping the sacrificial oxide, a thermal growth process produces a thicker oxide in the implanted regions (T2) than in the non-implanted regions (T1). The oxygen-implanted oxide has excellent quality and thickness differentials of up to 20 A may be obtained with relatively low oxygen implant doses. In an alternative process (1D-E), a thin gate oxide (12) may be grown prior to a polysilicon layer deposition (18), and oxygen is then implanted through the polysilicon according to a patterned photoresist mask. After stripping the photoresist, an anneal increases the thickness of the gate oxide in the implanted regions. In another embodiment, a high dielectric constant dielectric layer is deposited on the subsrate prior to polysilicon deposition to limit subsequent silicon oxide growth.

Multiple-thickness gate oxide formed by oxygen implantation

Hot-carrier-limited device lifetime of surface-channel p-MOSFETs is found to correlate well with gate current over a wide range of bias. The same result is not observed for buried-channel p-MOSFETs. A gate current model for surface-channel p-MOSFETs is presented. Using this gate current model, reasonable estimates of AC stress lifetime can be made based on DC stress data. >

Chenming Hu

Papers

Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition

Modeling of nonlinear thermal resistance in FinFETs

An advanced surface-potential-plus MOSFET model

Multiple-thickness gate oxide formed by oxygen implantation

p-MOSFET gate current and device degradation