Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Journal ArticleDOI
A methodology for the identification of worst-case test vectors for logical faults induced in CMOS circuits by total dose
TL;DR: In this article, a new methodology was developed for the identification of the worst-case combination of irradiation and postirradiation test vectors, which significantly simplifies total-dose testing of CMOS VLSI devices.
Journal ArticleDOI
Deterministic built-in self-test using split linear feedback shift register reseeding for low-power testing
TL;DR: Experimental results for the largest ISCAS'89 benchmark circuits show that the proposed scheme can reduce the switching activity by 50% with little hardware overhead compared with previous schemes.
Journal ArticleDOI
Design of efficient BIST test pattern generators for delay testing
Chih-Ang Chen,S.K. Gupta +1 more
TL;DR: Theoretical results and procedures are presented to design efficient TPGs that ensure high two-pattern coverage for comprehensive delay testing of a circuit under test (CUT) and the results demonstrate their effectiveness.
Journal ArticleDOI
Fault simulation for multiple faults by Boolean function manipulation
TL;DR: A fault simulation technique for multiple faults based on a deductive fault simulation method that assigns a distinct code word to each multiple fault and represents the fault by a minterm corresponding to its code word, which effectively handles multiple faults at significantly lower computation cost.
Proceedings ArticleDOI
Test generation for acyclic sequential circuits with hold registers
TL;DR: The hardware overhead for partial scan based on the proposed structure is smaller than that based on balanced or acyclic sequential structure without hold registers.