Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Dissertation
FSM state-assignment for area, power and testability using non-deterministic evolutionary heuristics
TL;DR: English) xvii Abstract (Arabic) XviiiArabic Arabic xviii as discussed by the authors, Arabic Arabic Arabic Xvii, English English Arabic XVIII.
Journal ArticleDOI
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations
TL;DR: Experimental results indicate that the MLVC method has very low runtimes, with excellent accuracy compared to existing approaches, and the comparison of the mean and standard deviation of the circuit leakage values for MLVC with MLVC-VAR and an existing random vector generating approach proves the need for considering these variations while determining the minimum leakage vector.
Proceedings ArticleDOI
Overcoming post-silicon validation challenges through quick error detection (QED)
TL;DR: An overview of QED is presented and it is presented that QED enables 2- to 4-fold improvement in bug coverage and does not require any hardware modification, making it readily applicable to existing designs.
Journal ArticleDOI
Accurate X-Propagation for Test Applications by SAT-Based Reasoning
TL;DR: An efficient method is presented for overcoming the pessimism of classic algorithms and for determining accurately the set of signals that carry an X-value for an input pattern and overmasking of test data during test compression can be reduced by an accurate analysis.
Journal ArticleDOI
C-testable bit parallel multipliers over GF(2m)
TL;DR: A C-testable design of polynomial basis (PB) bit-parallel (BP) multipliers over GF(2m) for 100% coverage of stuck-at faults and a Built-In Self-Test (BIST) architecture for generating the test vectors efficiently, which eliminates the need for the extra control inputs.