Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
An emulation model for sequential ATPG-based bounded model checking
TL;DR: A novel architecture to emulate the state-justification on reconfigurable hardware with the feature of fine-grain massive parallelism of reconfiguring hardware is exploited to achieve speed-up.
Proceedings ArticleDOI
A Novel BIST TPG for Testing of VLSI Circuits
TL;DR: A novel test pattern generator (TPG) is proposed which is more suitable for built in self test (BIST) architecture, used for testing of VLSI circuits, which shows a considerable reduction in number of CMOS devices and test power is achieved over the LFSR-TPG.
Journal ArticleDOI
High-Level Test Synthesis: A Survey from Synthesis Process Flow Perspective
Selvaraj Ravi,M. Joseph +1 more
TL;DR: A detailed survey on recent developments in high-level test synthesis from a synthesis process flow perspective and a survey on controller synthesis techniques for testability are presented.
Proceedings ArticleDOI
A Hamming distance based test pattern generator with improved fault coverage
TL;DR: A new test pattern generator (TPG) which is an enhancement of GLFSR (Galois LFSR), based on certain non-binary error detecting codes, formulated over an extension field of GF(2/sup/spl delta//), /spl delta/ > 1.
Journal ArticleDOI
A wafer level testability approach based on an improved scan insertion technique
Cristiana Bolchini,Giacomo Buonanno,Fabrizio Ferrandi,Donatella Sciuto,M. Bombana,P. Cavalloro +5 more
TL;DR: In this article, the authors introduce a structured approach to the design of testable wafer scale devices, in which the testability is guaranteed through the application mainly of the partial scan methodology, to provide the most convenient solution in terms of overhead and performance.