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Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Journal ArticleDOI
Concurrency-oriented verification and coverage of system-level designs
TL;DR: This work develops an automated framework complete with concurrency-oriented verification and coverage techniques for system-level designs and presents a comprehensive list of mutation operators for SystemC, similar to behavioral fault models, and shows the effectiveness of these operators by relating them to actual bug patterns.
Proceedings ArticleDOI
Dynamic power minimization during combinational circuit testing as a traveling salesman problem
TL;DR: This work focuses on the fact that power minimization is a traveling salesman problem (TSP), and explores application of local search and genetic algorithms to test set reordering and performs a quantitative comparison to previously used deterministic techniques.
Journal ArticleDOI
Algorithm for the generation of SIC pairs and its implementation in a BIST environment
TL;DR: A novel algorithm for the generation of SIC pairs is presented, termed decoder-based SIC pair generation (DSG) algorithm, and the number of memory elements utilised is the lowest reported in the literature.
Proceedings ArticleDOI
High-level fault modeling in surface-micromachined MEMS
N. Deb,R.D. Blanton +1 more
TL;DR: In this paper, the authors compared the results of schematic-level fault simulations with low-level finite element analysis and demonstrated the efficacy of such an approach and achieved a 60X speedup over FEA with little accuracy loss in modeling defects caused by particles.
Proceedings ArticleDOI
Mutation Operators for Concurrent SystemC Designs
TL;DR: This paper proposes a fault model by developing mutation operators for concurrent SystemC designs and aims to reap benefits of mutation testing for SystemC.