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Digital Systems Testing and Testable Design
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TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
TG-PRO: A new model for SAT-based ATPG
Huan Chen,Joao Marques-Silva +1 more
TL;DR: The proposed model is fundamentally different from previous SAT-based ATPG models in that the number of used variables is significantly reduced, and allows significant performance improvements over other well-established models.
Book ChapterDOI
Inducing Diagnostic Inference Models from Case Data
TL;DR: This chapter discusses an approach to analyzing a diagnostic case base and inducing a compact knowledge base using the diagnostic inference model with which efficient diagnostics can be performed, and applies a approach to reasoning using Dempster-Shafer theory to improve the diagnostics further.
Journal ArticleDOI
Autonomic microprocessor execution via self-repairing arrays
TL;DR: This paper develops two particular schemes for self-repairing array structures (SRAS) with less hardware overhead cost than higher-level redundancy and without the per-error performance penalty of existing low-cost techniques that combine error detection with pipeline flushes for backward error recovery.
Proceedings ArticleDOI
Off-line Testing of Crosstalk Induced Glitch Faults in NoC Interconnects
TL;DR: A methodology for at-speed testing of glitch faults in links connecting two distinct clock domains in a SoC or a NoC system using maximum number of aggressors to induce a glitch in the link to be tested for faults and use a latch to record this glitch.
Proceedings ArticleDOI
A test generation method using a compacted test table and a test generation method using a compacted test plan table for RTL data path circuits
TL;DR: The proposed methods could shorten test lengths for some RTL data path circuits compared with the conventional hierarchical test generation method.