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Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Book ChapterDOI
Electrical Testing of Multichip Modules
Thomas C. Russell,Yenting Wen +1 more
TL;DR: Electrical testing is used throughout the multichip module fabrication process to verify the quality of each processing step and component which goes into the module.
Proceedings ArticleDOI
Compact and complete test set generation for multiple stuck-faults
TL;DR: In this paper, a branch and bound procedure is used to generate test sets for multiple stuck-faults in a logic circuit, independent of the occurrence of other faults, and the technique is complete and applies to all circuits.
Proceedings ArticleDOI
Using ATPG for clock rules checking in complex scan designs
P. Wohl,J. Waicukauski +1 more
TL;DR: A robust set of clock rules and their implementation for scan designs are defined and clock-rule-violation detection beyond test requirements is extended, which provides fast clock verification early in the design cycle, complementing the more complex and slower timing tools.
Proceedings ArticleDOI
Testing high-speed SoCs using low-speed ATEs
Mehrdad Nourani,J. Chin +1 more
TL;DR: An ILP formulation is presented to globally optimize such coordination in terms of the overall test time and the hardware cost.
Proceedings ArticleDOI
An adjacency-based test pattern generator for low power BIST design
TL;DR: A new BIST TPG design that is comprised of an Adjacency-based TPG plus a conventional pseudo-random TPG (i.e. a LFSR) is presented in this paper, which reduces the number of transitions that occur in the CUT and hence decreases the average and peak power consumption during testing.