Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
Citations
More filters
Journal ArticleDOI
Protection Against Hardware Trojan Attacks: Towards a Comprehensive Solution
Swarup Bhunia,Miron Abramovici,Dakshi Agrawal,Paul Bradley,Michael S. Hsiao,Jim Plusquellic,Mohammad Tehranipoor +6 more
TL;DR: An overview of hardware Trojans and countermeasures is provided that act as spies or terrorists in the microelectronic industry.
Proceedings ArticleDOI
Diagnosis of realistic bridging faults with single stuck-at information
TL;DR: The original technique is analyzed and improved by introducing the concepts of match restriction, match requirement, and failure recovery, which produces diagnoses that are an order of magnitude smaller than those produced by the original technique and produces many fewer misleading diagnoses than that of traditional stuck-at diagnosis.
Proceedings ArticleDOI
Fault diagnosis and logic debugging using Boolean satisfiability
TL;DR: This work proposes a model-free satisfiability-based solution to Fault diagnosis and logic debugging for digital VLSI design problems and shows that satisfiability captures significant problem characteristics and it offers different trade-offs.
Proceedings ArticleDOI
Boolean satisfiability in electronic design automation
TL;DR: This tutorial paper is aimed at introducing the EDA professional to the Boolean satisfiability problem, and highlights the use of SAT models to formulate a number of EDA problems in such diverse areas as test pattern generation, circuit delay computation, logic optimization, combinational equivalence checking, bounded model checking and functional test vector generation.
Journal ArticleDOI
Constructing Online Testable Circuits Using Reversible Logic
S.N. Mahammad,K. Veezhinathan +1 more
TL;DR: A novel universal reversible logic gate (URG) and a set of basic sequential elements that could be used for building reversible sequential circuits, with 25% less garbage than the best reported in the literature are proposed.