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Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency
Ian G. Harris,Alex Orailoglu +1 more
TL;DR: Experimental results show that designs generated by this approach are testable in a highly concurrent manner.
Proceedings ArticleDOI
Error catch and analysis for semiconductor memories using march tests
TL;DR: An error catch and analysis system for semiconductor memories that consists of a test algorithm generator called TAGS, a fault simulator called RAMSES, and an error analyzer that is able to support March algorithms for easy diagnosis of faulty RAMs is presented.
Proceedings ArticleDOI
Automatic test generation using genetically-engineered distinguishing sequences
TL;DR: In the new test generator, DIGATE, genetic algorithms are used to derive both activating and distinguishing sequences during test generation, which shows very high fault coverages for the ISCAS89 sequential benchmark circuits and several synthesized circuits.
Journal ArticleDOI
Resource-constrained system-on-a-chip test: a survey
Qiang Xu,Nicola Nicolici +1 more
TL;DR: A survey of the recent advances in resource-constrained core-based SOC test is presented, which highlights the need to consciously use the resources at hand, while keeping the testing time and volume of test data under control.
Proceedings ArticleDOI
Fast Boolean optimization by rewiring
TL;DR: The algorithm applies the reasoning of Automatic Test Pattern Generation (ATPG) which can detect redundancy efficiently and analyzes different characteristics of mandatory assignments during the ATPG process to find the most efficient Boolean logic optimization method.