Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Patent
Block based design methodology with programmable components
TL;DR: In this paper, a method for designing a circuit block includes the steps of selecting a plurality of pre-designed circuit blocks to be used to design the circuit system, at least one of said circuit blocks being programmable.
Journal ArticleDOI
Fault diagnosis of electronic systems using intelligent techniques: a review
TL;DR: This paper reviews this research, primarily covering rule-based, model- based, and case-based approaches and applications, which may lead to a greater acceptance of automated diagnosis.
Proceedings ArticleDOI
Low Power Error Resilient Encoding for On-Chip Data Buses
TL;DR: It is shown that retransmission strategies are more effective than correction ones from an energy viewpoint, both for the larger detection capability and for the minor decoding complexity.
Proceedings ArticleDOI
Carafe: an inductive fault analysis tool for CMOS VLSI circuits
A. Jee,F.J. Ferguson +1 more
TL;DR: The Carafe software package is discussed, which determines which faults are likely to occur in a circuit based on the circuit's physical design, defect parameters, and fabrication technology.
Patent
3D semiconductor device and structure
TL;DR: In this article, an Integrated Circuit device including a first layer including first single crystal transistors; a second layer overlaying the first layer, the second layer including second single-crystal transistors, where the second-layer thickness is less than one micron, where a plurality of the first transistors is circumscribed by a first dice lane of at least 10 microns width, and there are no first conductive connections to the plurality of transistors that cross the first-dice lane.