Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
Citations
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Book ChapterDOI
On bridging simulation and formal verification
TL;DR: The notion of a sufficient test set of a CNF formula as a test set encrypting a formal proof that this formula is unsatisfiable is introduced and it is shown how sufficient test sets can be built.
Proceedings ArticleDOI
Nonlinear CA based design of test set generator targeting pseudo-random pattern resistant faults
TL;DR: The design of an efficient test set generator (TSG) for VLSI circuit is built around the regular structure of cellular automata (CA) employing nonlinear CA rules and targets detection of hard-to-detect pseudo-random pattern resistant faults.
Proceedings ArticleDOI
Test pattern generation for power supply droop faults
Debasis Mitra,Subhasis Bhattacharjee,Susmita Sur-Kolay,Bhargab B. Bhattacharya,S.T. Zachariah,S. Kunduc +5 more
TL;DR: A new model for droop faults is proposed and experimental results on ISCAS-85 benchmark circuits reveal that a very high droop fault coverage can be obtained by a short sequence of test vectors.
Proceedings ArticleDOI
Design and synthesis for testability of synchronous sequential circuits based on strong-connectivity
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: The importance of strong-connectivity of the state diagram of a circuit in ensuring testability, specifically, in ensuring that no partially detectable faults exist, is shown.
Journal ArticleDOI
Input Necessary Assignments for Testing of Path Delay Faults in Standard-Scan Circuits
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: The proposed test generation procedure is able to resolve large numbers of path delay faults associated with the longest paths in benchmark circuits by detecting the faults using broadside tests or showing that they are undetectable by such tests.