Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
Citations
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Journal ArticleDOI
Built-In Generation of Functional Broadside Tests Using a Fixed Hardware Structure
TL;DR: This paper shows that on-chip generation of functional broadside tests can be done using a simple and fixed hardware structure, with a small number of parameters that need to be tailored to a given circuit, and can achieve high transition fault coverage for testable circuits.
Boolean Satisfiability Solvers: Techniques and Extensions.
Georg Weissenbacher,Sharad Malik +1 more
TL;DR: Boolean Satisfiability (SAT) is the problem of checking if a propositional logic formula can ever evaluate to true and manifests itself in several important application domains such as the design and verification of hardware and software systems, as well as applications in artificial intelligence.
Patent
Systems and methods for signature circuits
TL;DR: Signature circuits as discussed by the authors store a signature for the circuit under test based on a combination of signals from the circuit in response to test vectors and a previous stored state of the signature register.
Proceedings ArticleDOI
On the Mutation Analysis of SystemC TLM-2.0 Standard
TL;DR: This paper discusses on the mutation analysis concept applied to the TLM context and proposes a mutation model for perturbing TLM SystemC descriptions, and a set of mutants is proposed to perturb the primitives related to theTLM communication interfaces.
Proceedings ArticleDOI
Design, verification, and test of a true single-phase 8-bit adiabatic multiplier
TL;DR: In HSPICE simulations with post-layout extracted parasitics, the design functions correctly at frequencies exceeding 200 MHz, with total dissipation for the multiplier and BIST circuitary of 91 pJ per multiplication at 100 MHz.