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Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Proceedings ArticleDOI
ATPG for heat dissipation minimization during test application
TL;DR: A new ATPG algorithm has been proposed that reduces average heat dissipation (between successive test vectors) during test application to permit safe and inexpensive testing of low power circuits and bare dies that would otherwise require expensive heat removal equipment for testing at high speeds.
Proceedings ArticleDOI
Using roving STARs for on-line testing and diagnosis of FPGAs in fault-tolerant applications
TL;DR: A new fault-tolerant (FT) technique allows using partially defective FPGA resources for normal operation, providing longer mission life-span in the presence of faults, and the basic concepts of a new dynamic FT method are introduced.
Proceedings ArticleDOI
A modified clock scheme for a low power BIST test pattern generator
Patrick Girard,L. Guiller,Christian Landrault,Serge Pravossoudovitch,Hans-Joachim Wunderlich +4 more
TL;DR: A new low power test-per-clock BIST test pattern generator that provides test vectors which can reduce the switching activity during test operation and numerous advantages can be found in applying such a technique during BIST.
Proceedings ArticleDOI
CRIS: a test cultivation program for sequential VLSI circuits
TL;DR: An approach to cultivating a test for combinational and sequential VLSI circuits described hierarchically at the transistor, gate, and higher levels is discussed, based on continuous mutation of a given input sequence and on analyzing the mutated vectors for selecting the test set.
Proceedings ArticleDOI
Satisfiability-based layout revisited: detailed routing of complex FPGAs via search-based Boolean SAT
TL;DR: A new search-based Satisfiability (SAT) formulation that can handle entire FPGAs, routing all nets concurrently, relies on a recently developed SAT engine that uses systematic search with conflict-directed non-chronological backtracking, capable of handling very large SAT instances.