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Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
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Constraint Solving over Multi-Valued Logics: Application to Digital Circuits
TL;DR: A “black-box” system modelled by a set of propositional logic rules, in which just a subset of components is externally visible, such faults may only be recognised by examining some output function of the system.
Journal ArticleDOI
A Two-Variable Model for SAT-Based ATPG
Huan Chen,Joao Marques-Silva +1 more
TL;DR: Experimental results demonstrate that the basic model and extended models allow significant performance improvements over other well-established models and integrates known techniques for further improving performance.
Proceedings ArticleDOI
AND/OR reasoning graphs for determining prime implicants in multi-level combinational networks
TL;DR: It will be demonstrated that AND/OR reasoning graphs allow us to naturally extend basic notions of two-level switching circuit theory to multi-level circuits and it is proved that and/or reasoning graphs represent all these implicants.
Line Oriented Structural Equivalence Fault Collapsing
TL;DR: In this paper, a new perspective on structural fault collapsing at the gate level is presented, which enables a faster and optionally a more reduced fault collapsing, and is easily implementable in the VHDL language.
Proceedings ArticleDOI
A BIST scheme for the detection of path-delay faults
TL;DR: The proposed technique is based on an existing BIST architecture for stuck-at faults such that timing faults in a circuit can also be addressed with minimum additional effort and experimental results show high path-delay fault coverage for sequential circuits.