Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
Citations
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Proceedings ArticleDOI
An exact solution to the minimum size test pattern problem
TL;DR: This paper addresses the problem of test pattern generation for single stuck-at faults in combinational circuits, under the additional constraint that the number of specified primary input assignments is minimized.
Journal ArticleDOI
Design-for-testability for path delay faults in large combinational circuits using test points
Irith Pomeranz,Sudhakar M. Reddy +1 more
TL;DR: A method for test-point insertion in large combinational circuits, to increase their path delay fault testability and to demonstrate the effectiveness of the proposed methods in increasing the testability of large benchmark circuits.
Proceedings ArticleDOI
MUST: multiple-stem analysis for identifying sequentially untestable faults
TL;DR: It is shown that the faults identified by MUST are difficult targets for conventional ATPG programs, that can benefit by using MUST as a preprocessor and excluding the untestable faults identify by multiple stem analysis from the target faults processed by ATPG.
Patent
Methods for distributing programs for generating test data
TL;DR: In this paper, the authors describe methods and systems for distributed execution of circuit testing algorithms, or portions thereof, over a network of plurality of processors, including a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own.
Proceedings ArticleDOI
Automatic scan insertion and test generation for asynchronous circuits
TL;DR: A test method for asynchronous handshake circuits is presented that is based on synchronous full-scan techniques, which resulted in an operational flow, capable of automatically testing any handshake circuit with test-quality equal to synchronous circuits.