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Digital Systems Testing and Testable Design

TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.
Abstract
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.

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Proceedings ArticleDOI

Two techniques for minimizing power dissipation in scan circuits during test application

TL;DR: Two techniques for reducing power dissipation during test application, when scan test structure is used, are proposed and are shown to be intractable.
Proceedings ArticleDOI

Perturb and simplify: multi-level boolean network optimizer

TL;DR: This paper proposes several new ways in which one or more redundant gates or wires can be added to a network and addresses the problem of efficient redundancy computation which allows to eliminate many unnecessary redundancy tests.
Journal ArticleDOI

Automatic test pattern generation for functional register-transfer level circuits using assignment decision diagrams

TL;DR: An algorithm for generating test patterns automatically from functional register-transfer level (RTL) circuits that target detection of stuck-at faults in the circuit at the logic level, using a data structure named assignment decision diagram that has been proposed previously in the field of high-level synthesis.
Proceedings ArticleDOI

Design of compactors for signature-analyzers in built-in self-test

TL;DR: This paper analyzes how compactors affect test and diagnosis and shows that compactors can be designed to actually improve the testability of certain faults, while providing full diagnosis capability.
Journal ArticleDOI

Classification of faults in synchronous sequential circuits

TL;DR: Undetectable and redundant faults in synchronous sequential circuits are analyzed and a distinction is drawn between undetectable faults and faults that are never manifested as output errors.