Open AccessBook
Digital Systems Testing and Testable Design
TLDR
The new edition of Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems offers comprehensive and state-ofthe-art treatment of both testing and testable design.Abstract:
For many years, Breuer-Friedman's Diagnosis and Reliable Design ofDigital Systems was the most widely used textbook in digital system testing and testable design. Now, Computer Science Press makes available a new and greativ expanded edition. Incorporating a significant amount of new material related to recently developed technologies, the new edition offers comprehensive and state-ofthe-art treatment of both testing and testable design.read more
Citations
More filters
Journal ArticleDOI
Analog testing by characteristic observation inference
TL;DR: The COI method applied to two different test designs yields very good results with respect to parametric faults as well as to catastrophic faults, and a physically interpretable sampling strategy is presented.
Proceedings ArticleDOI
A new algorithm for global fault collapsing into equivalence and dominance sets
TL;DR: Examples show how more compact fault sets are obtained by using functional equivalences that can be found by analysis of small cells.
Proceedings ArticleDOI
CAEN-BIST: testing the nanofabric
J.G. Brown,R.D. Blanton +1 more
TL;DR: In this paper, a self-test algorithm for chemically-assembled electronic nanotechnology (CAEN) was developed that exploits reconfigurability to achieve 100% fault coverage and nearly 100% diagnostic accuracy.
Proceedings ArticleDOI
Analyzing Fault Models for Reversible Logic Circuits
Jing Zhong,Jon C. Muzio +1 more
TL;DR: In this article, a new fault model, labeled crosspoint faults, is proposed for reversible logic circuits and a randomized Automatic Test Pattern Generation algorithm targeting this specific kind of fault is introduced and analyzed.
Dissertation
Search algorithms for satisfiability problems in combinational switching circuits
TL;DR: A configurable search-based algorithm for SAT that can be used for implementing different circuit analysis tools and a new model for path sensitization that permits modeling test pattern generation and timing analysis with linear size representations are introduced.