Institution
STMicroelectronics
Company•Geneva, Switzerland•
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.
Topics: Signal, Transistor, Layer (electronics), Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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29 Jul 1994TL;DR: In this paper, the input buffer of an integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means.
Abstract: According to the present invention, an integrated circuit device is capable of responding to more than one input threshold voltage level by making only minimal changes to the device. The input buffer of the integrated circuit device is modified to be a programmable buffer that is controlled by a control input signal which may be generated by several different control means. Such control means include a bond option, a mask option, a fuse option, a register option, and a voltage detector option.
54 citations
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11 Dec 1996TL;DR: In this paper, a circuit including a network of capacitors and switching transistors having two modes of functioning, isolating all the capacitors, and simultaneously charging them to the level of the supply voltage, is described.
Abstract: A circuit including a network of capacitors and switching transistors having two modes of functioning. The first mode isolates all the capacitors and simultaneously charges them to the level of the supply voltage. The second mode connects all these capacitors in series between the supply voltage Vdd and an output node of the network in order to instantaneously increase the voltage level of this output node to a voltage level that is greater than the supply voltage Vdd. The capacitors are all connected in series by transistors that are placed between them and controlled by a signal that has a peak voltage that is greater than the voltage to be switched to the output node of the network.
54 citations
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18 Mar 2005TL;DR: In this article, the authors propose a method to encode/decode a video signal sequence by generating therefrom multiple description subsequences wherein the subsequences are produced by a plurality of parallel video encoding processes based on respective encoding parameters.
Abstract: The method is directed to encoding/decoding a video signal sequence by generating therefrom multiple description subsequences wherein the subsequences are produced by a plurality of parallel video encoding processes based on respective encoding parameters. The method includes the step of commonly controlling the encoding/decoding parameters for the plurality of video encoding/decoding processes.
54 citations
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07 Jun 1995TL;DR: In this article, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitsline.
Abstract: In a high density memory, such as a SRAM, DRAM, EPROM or EEPROM, a hierarchical bitline configuration is utilized such that a number of local bitlines are connected to a master bitline through interface circuitry which connects a local bitline to the master bitline. Local select signals, when set to the appropriate voltage level, couple a local bitline to the master bitline. In addition to reducing the local bitline capacitance that must be driven by memory cells, the hierarchical configuration may provide layout area savings as well. Interface circuitry is modified to provide voltage and signal gain and/or provide isolation between the local bitlines and the master bitlines, thereby reducing the amount of capacitance which must be driven by memory cells and the amount of time required to develop differential signals on the master bitlines.
54 citations
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13 Mar 2006TL;DR: In this paper, the authors present a single pole 6-throw antenna switch able to manage all the four GSM standards, i.e. 850-900-1800-1900 MHz.
Abstract: This paper presents the design of a single pole 6 throw antenna switch able to manage all the four GSM standards, i.e. 850-900-1800-1900 MHz. The switch has been integrated in a 0.13/spl mu/m CMOS SOI process with high resistivity substrate and a thick oxide (50/spl Aring/) option. The use of high resistivity substrate allows a good loss (IL)-isolation trade-off: IL is kept in the range of 0.55-0.8 dB for the RXs and at 0.7 dB for the TXs, while isolation varies from 40 dB at 900 MHz to 30 dB at 1900 MHz. Power handling capability is well compatible with GSM standards since an ICP/sub 0.1dB/ of 36 dBm has been measured and harmonics distortion is below -39 dBm for an input power of 34 dBm. Robustness to antenna mismatching condition has been successfully demonstrated up to a VSWR of 10:1. The chip size is of 1.23 mm/sup 2/ and the power consumption is below 10/spl mu/A and 0.5 mA respectively in stand by mode and during switching, under 2.5 voltage supply.
54 citations
Authors
Showing all 17185 results
Name | H-index | Papers | Citations |
---|---|---|---|
Bharat Bhushan | 116 | 1276 | 62506 |
Albert Polman | 97 | 445 | 42985 |
G. Pessina | 84 | 828 | 30807 |
Andrea Santangelo | 83 | 886 | 29019 |
Paolo Mattavelli | 74 | 482 | 19926 |
Daniele Ielmini | 68 | 367 | 16443 |
Jean-François Carpentier | 62 | 459 | 14271 |
Robert Henderson | 58 | 440 | 13189 |
Bruce B. Doris | 56 | 604 | 12366 |
Renato Longhi | 55 | 177 | 8644 |
Aldo Romani | 54 | 425 | 11513 |
Paul Muralt | 54 | 344 | 12694 |
Enrico Zanoni | 53 | 705 | 13926 |
Gaudenzio Meneghesso | 51 | 703 | 12567 |
Franco Zappa | 50 | 274 | 9211 |