STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

An Overview of Patterned Metal/Dielectric Surface Bonding: Mechanism, Alignment and Characterization

Abstract: An overview of the different metal bonding techniques used for 3D integration is presented. Key parameters such as surface preparation, temperature and duration of annealing, achievable wafer-to-wafer alignment and electrical results are reviewed. A special focus is done on direct bonding of patterned metal/dielectric surfaces. A mechanism for copper direct bonding is proposed based on bonding toughness measurements, SAM, XRR, XRD, and TEM analysis. Dedicated characterization techniques for such bonding are presented.

H-matrix for error correcting circuitry

Abstract: A matrix H for encoding data words is defined for wide word ECC with uniform density and a reduced number of components. The H-matrix is incorporated in an encode unit operable to Hamming encode a data word with a 10×528 matrix generated in groups of four columns wherein; a first column is a complement of a second column; the value of the second column ranges from 9 to 271 in increments of two; a third column is a complement of a fourth column; and the value of the fourth column is the same as the value of the second column less one; and wherein a 528-bit bottom row is added to the 10×528 matrix comprising alternating zeroes and ones starting with a zero creating an 11×528 matrix.

Data Retention Characterization of Phase-Change Memory Arrays

Abstract: To support reliable large array products, phase-change memory (PCM) technologies must be able to retain data over the product's lifetime with very low defect rates. PCM stores data in a chalcogenide material which can be placed in either a high resistance amorphous phase or a low resistance crystalline phase. Data retention is limited by resistance loss of the amorphous phase of the material, a process that is controlled by the kinetics of crystallization. This paper presents array-level data retention results on a statistical distribution of PCM cells that shows the failure rate with temperature to be well-described by the Arrhenius equation and distributed lognormally with time. For typical cells, the retention capability exceeds 100,000 hours at 85degC and is capable of meeting product requirements. In non-optimized devices, however, we observe cells that fail earlier than the lognormal distribution would predict. The failure distribution of these cells is Weibull with time but shows similar temperature acceleration to the intrinsic distribution, indicative of a defect in the amorphous chalcogenide. Characterization of these cells shows that their retention behavior is erratic. Furthermore, it is not significantly changed by write cycling. We then show that this defect distribution can be suppressed by process architecture or write algorithm optimization. Retention data collected on cells at both the 180nm and 90nm lithography nodes show that the intrinsic behavior is maintained with process scaling

Filtering of noisy images

Abstract: A method for correcting an image from defects and filtering from Gaussian noise corrects each pixel of the image when it is considered defective and filters it from Gaussian noise in one-pass. The one-pass improves the speed for performing the correcting and filtering. The drawbacks associated with choosing incompatible defect correction and filtering operations are overcome.

Architecture of a low-complexity non-binary LDPC decoder for high order fields

Abstract: In this paper, we propose a hardware implementation of the EMS decoding algorithm for non-binary LDPC codes, presented in [10]. To the knowledge of the authors this is the first implementation of a GF(q) LDPC decoder for high order fields (q ges 64). The originality of the proposed architecture is that it takes into account the memory problem of the non-binary LDPC decoders, together with a significant complexity reduction per decoding iteration which becomes independent from the field order. We present the estimation of the non-binary decoder implementation and key metrics including throughput and hardware complexity. The error decoding performance of the low complexity algorithm with proper compensation has been obtained through computer simulations. The frame error rate results are quite good with respect to the important complexity reduction. The results show also that an implementation of a non-binary LDPC decoder is now feasible and the extra complexity of the decoder is balanced by the superior performance of this class of codes. With their foreseen simple architectures and good-error correcting performances, non-binary LDPC codes provide a promising vehicle for real-life efficient coding system implementations.