STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

A 94-GHz 4TX–4RX Phased-Array FMCW Radar Transceiver With Antenna-in-Package

Abstract: A 94-GHz phased-array transceiver IC for frequency modulated continuous wave (FMCW) radar with four transmitters, four receivers, and integrated LO generation has been designed and fabricated in a 130-nm SiGe BiCMOS technology, and integrated into an antenna-in-package module. The transceiver, targeting gesture recognition applications for mobile devices, has been designed using phased-array techniques to reduce the total DC power while still maintaining the required link budget for FMCW operation. The complete array achieves state-of-the-art for W-band per-element power consumption of 106 mW per TX element and 91 mW per RX element, and measurements indicate a per-element output power of 6.4 dBm and single-sideband noise figure of 12.5 dB at 94 GHz. The array is able to achieve a beam steering range of ±20° while maintaining at least 3 dB main lobe to side lobe levels. The complete chip-antenna module has been tested to characterize basic FMCW radar functionality. Initial radar experiments suggest a sub-5-cm range resolution is possible with 3.68 GHz RF sweep bandwidth, which is in line with theoretical predictions.

Programmable summing functions for programmable logic devices

Abstract: A programmable logic device includes a programmable logic array and an output logic macrocell The output logic macrocell includes a user configurable summing function that has a first logic gate connected to receive a first plurality of product terms, a second logic gate connected to receive a second plurality of product terms and a third logic gate connected to receive the combination of the first plurality of product terms and a controls signal, a fourth logic gate connected to receive the combination of the second plurality of Product Terms and the control signal and a logic circuit connected to receive the output signals from the first, second, third and fourth logic gates and to provide a first logical combination when the control signal is at a first logic state and a second logical combination when the controls signal is at a second logic state

Page-erasable flash memory

Abstract: The invention concerns a page-erasable flash memory (MEM1) comprising a memory plane (FMA) including a plurality of pages comprising each floating gate transistors connected by their gates to word lines (WL1), a word line decoder (XDEC1) connected to the memory word lines, and means for applying a positive erasing voltage (VER+) to the source or drain electrodes of all the floating gate transistors of a sector comprising a page to be erased. The invention is characterised in that the word line decoder (XDEC1) comprises means (ADi) for applying, during erasure of a page, a negative erasing voltage (VPOL, VER-) to the gates of the transistors of the page to be erased, while applying a positive inhibiting voltage (VINHIB, VPCX) to the gates of the transistors of at least one page not to be erased. The memory also comprises means controlling at least a page of the memory, designed to perform a first reading of the page by applying a first reading voltage (VREAD) to the gates of the transistors of the page, perform a second reading of the page by applying a second reading voltage (VVRFY) to the gates of the transistors of the page, and reprogram transistors of the page if the two readings yield different results (W1, W2).

Method of forming raised source/drain regions in an integrated circuit

Abstract: A method is provided for forming a planar transistor of a semiconductor integrated circuit, and an integrated circuit formed according to the same. A plurality of field oxide regions are formed overlying a substrate electrically isolating a plurality of transistors encapsulated in a dielectric. LDD regions are formed in the substrate adjacent the transistors and the field oxide regions. Doped polysilicon raised source and drain regions are formed overlying the LDD regions and a tapered portion of the field oxide region and adjacent the transistor. These polysilicon raised source and drain regions will help to prevent any undesired amount of the substrate silicon from being consumed, reducing the possibility of junction leakage and punchthrough as well as providing a more planar surface for subsequent processing steps.

Parallel programming models for a multiprocessor SoC platform applied to networking and multimedia

Abstract: The MultiFlex system is an application-to-platform mapping tool that integrates heterogeneous parallel components-H/W or S/W- into a homogeneous platform programming environment. This leads to higher quality designs through encapsulation and abstraction. Two high-level parallel programming models are supported by the following MultiFlex platform mapping tools: a distributed system object component (DSOC) object-oriented message passing model and a symmetrical multiprocessing (SMP) model using shared memory. We demonstrate the combined use of the MultiFlex multiprocessor mapping tools, supported by high-speed hardware-assisted messaging, context-switching, and dynamic scheduling using the StepNP demonstrator multiprocessor system-on-chip platform, for two representative applications: 1) an Internet traffic management application running at 2.5 Gb/s and 2) an MPEG4 video encoder (VGA resolution, at 30 frames/s). For these applications, a combination of the DSOC and SMP programming models were used in interoperable fashion. After optimization and mapping, processor utilization rates of 85%-91% were demonstrated for the traffic manager. For the MPEG4 decoder, the average processor utilization was 88%