Institution
STMicroelectronics
Company•Geneva, Switzerland•
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.
Topics: Signal, Transistor, Layer (electronics), Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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16 Feb 2004TL;DR: The simulation environment proved capable of a detailed comparative analysis between two industry-standard communication architectures, under realistic workloads and different system configurations, pointing out the impact of fine grained architectural mismatches on macroscopic performance differences.
Abstract: This work focuses on communication architecture analysis for multi-processor systems-on-chips (MPSoCs), and it leverages a SystemC-based platform to simulate a complete multi-processor system at the cycle-accurate and signal-accurate level. These features allow to stimulate the communication sub-system with functional traffic generated by real applications running on top of a configurable number of ARM processors. This opens up the possibility for communication infrastructure exploration and for the investigation of its impact on system performance at the highest level of accuracy. Our simulation environment proved capable of a detailed comparative analysis between two industry-standard communication architectures, under realistic workloads and different system configurations, pointing out the impact of fine grained architectural mismatches on macroscopic performance differences.
186 citations
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01 Dec 2011TL;DR: This paper addresses the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer and can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices.
Abstract: 3D sequential integration enables the full use of the third dimension thanks to its high alignment performance. In this paper, we address the major challenges of 3D sequential integration: in particular, the control of molecular bonding allows us to obtain pristine quality top active layer. With the help of Solid Phase Epitaxy, we can match the performance of top FET, processed at low temperature (600°C), with the bottom FET devices. Finally, the development of a stable salicide enables to retain bottom performance after top FET processing. Overcoming these major technological issues offers a wide range of applications.
184 citations
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07 Apr 2011TL;DR: A fully integrated WirelessHD compatible 60-GHz transceiver module in 65-nm CMOS process is presented, covering the four standard channels, targeting industrial manufacturability.
Abstract: This paper presents a fully integrated 60GHz transceiver module in a 65nm CMOS technology for wireless high-definition video streaming. The CMOS chip is compatible with the WirelessHD™ standard, covers the four channels and supports 16-QAM OFDM signals including the analog baseband. The ESD-protected die (9.3mm²) is flip-chipped atop a High Temperature Cofired Ceramic (HTCC) substrate, which receives also an external PA and the emission and reception glass-substrate antennas. The module occupies an area of only 13.5×8.5mm². It consumes 454mW in receiver mode and 1.357W in transmitter mode (357mW for the transmitter and 1W for the PA).
183 citations
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TL;DR: In this article, an ultra-compact indium phosphide-on-silicon laser diode with low current threshold, high wall-plug efficiency and high integrability is demonstrated.
Abstract: By exploiting one-dimensional photonic crystal nanocavities, an ultra-compact indium phosphide-on-silicon laser diode with low current threshold, high wall-plug efficiency and high integrability is demonstrated. The most-awaited convergence of microelectronics and photonics promises to bring about a revolution for on-chip data communications and processing1. Among all the optoelectronic devices to be developed, power-efficient nanolaser diodes able to be integrated densely with silicon photonics and electronics are essential to convert electrical data into the optical domain. Here, we report a demonstration of ultracompact laser diodes based on one-dimensional (1D) photonic crystal (PhC) nanocavities2,3,4 made in InP nanoribs heterogeneously integrated on a silicon-waveguide circuitry. The specific nanorib design enables an efficient electrical injection of carriers in the nanocavity without spoiling its optical properties. Room-temperature continuous-wave (CW) single-mode operation is obtained with a low current threshold of 100 µA. Laser emission at 1.56 µm in the silicon waveguides is obtained with wall-plug efficiencies greater than 10%. This result opens up exciting avenues for constructing optical networks at the submillimetre scale for on-chip interconnects and signal processing.
179 citations
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TL;DR: In this article, it was shown that the current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries, and that the characteristic current density also remains invariant for the most common circuit topologies such as MOS-SiGe HBT cascodes, MOS CML gates, and nMOS transimpedance amplifiers (TIAs) with active pMOS FET loads.
Abstract: This paper provides evidence that, as a result of constant-field scaling, the peak fT (approx. 0.3 mA/mum), peak fMAX (approx. 0.2 mA/mum), and optimum noise figure NFMIN (approx. 0.15 mA/mum) current densities of Si and SOI n-channel MOSFETs are largely unchanged over technology nodes and foundries. It is demonstrated that the characteristic current densities also remain invariant for the most common circuit topologies such as MOSFET cascodes, MOS-SiGe HBT cascodes, current-mode logic (CML) gates, and nMOS transimpedance amplifiers (TIAs) with active pMOSFET loads. As a consequence, it is proposed that constant current-density biasing schemes be applied to MOSFET analog/mixed-signal/RF and high-speed digital circuit design. This will alleviate the problem of ever-diminishing effective gate voltages as CMOS is scaled below 90 nm, and will reduce the impact of statistical process variation, temperature and bias current variation on circuit performance. The second half of the paper illustrates that constant current-density biasing allows for the porting of SiGe BiCMOS cascode operational amplifiers, low-noise CMOS TIAs, and MOS-CML and BiCMOS-CML logic gates and output drivers between technology nodes and foundries, and even from bulk CMOS to SOI processes, with little or no redesign. Examples are provided of several record-setting circuits such as: 1) SiGe BiCMOS operational amplifiers with up to 37-GHz unity gain bandwidth; 2) a 2.5-V SiGe BiCMOS high-speed logic chip set consisting of 49-GHz retimer, 40-GHz TIAs, 80-GHz output driver with pre-emphasis and output swing control; and 3) 1-V 90-nm bulk and SOI CMOS TIAs with over 26-GHz bandwidth, less than 8-dB noise figure and operating at data rates up to 38.8 Gb/s. Such building blocks are required for the next generation of low-power 40-80 Gb/s wireline transceivers
178 citations
Authors
Showing all 17185 results
Name | H-index | Papers | Citations |
---|---|---|---|
Bharat Bhushan | 116 | 1276 | 62506 |
Albert Polman | 97 | 445 | 42985 |
G. Pessina | 84 | 828 | 30807 |
Andrea Santangelo | 83 | 886 | 29019 |
Paolo Mattavelli | 74 | 482 | 19926 |
Daniele Ielmini | 68 | 367 | 16443 |
Jean-François Carpentier | 62 | 459 | 14271 |
Robert Henderson | 58 | 440 | 13189 |
Bruce B. Doris | 56 | 604 | 12366 |
Renato Longhi | 55 | 177 | 8644 |
Aldo Romani | 54 | 425 | 11513 |
Paul Muralt | 54 | 344 | 12694 |
Enrico Zanoni | 53 | 705 | 13926 |
Gaudenzio Meneghesso | 51 | 703 | 12567 |
Franco Zappa | 50 | 274 | 9211 |