STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

$Z$ -Axis Magnetometers for MEMS Inertial Measurement Units Using an Industrial Process

Abstract: The combination of multiaxis and multiparameter microelectromechanical systems (MEMS) in the same technology would result in very cheap and smart inertial measurement units (IMUs). In this paper, a $Z$ -axis Lorentz-force-based magnetometer whose design and optimization are reviewed taking into account the constraints of an industrial MEMS technology (process and packaging) already used for accelerometers and gyroscopes is presented. How this impacts the design guidelines is shown; in particular, a very compact device that can fit in the same package of the gyroscope to realize an all-MEMS seven-degree-of-freedom IMU is proposed and experimentally tested. The device shows a mechanical sensitivity of around 0.8 $\hbox{aF}/(\mu\hbox{T} \cdot \hbox{mA})$ with a resolution of 520 $(\hbox{nT} \cdot \hbox{mA})/\sqrt{\hbox{Hz}}$ over a signal bandwidth of 50 Hz at room temperature. Coupled to a transimpedance amplifier, the system shows an overall sensitivity of 150 $\mu\hbox{V}/\mu\hbox{T}$ at 250 $\mu\hbox{A}$ of peak driving current.

Low loss 40 Gbit/s silicon modulator based on interleaved junctions and fabricated on 300 mm SOI wafers

Abstract: We demonstrate high-speed silicon modulators based on carrier depletion in interleaved pn junctions fabricated on 300mm-SOI wafers using CMOS foundry facilities. 950µm-long Mach Zehnder (MZ) and ring resonator (RR) modulator with a 100µm radius, were designed, fabricated and characterized. 40 Gbit/s data transmission has been demonstrated for both devices. The MZ modulator exhibited a high extinction ratio of 7.9 dB with only 4 dB on-chip losses at the operating point.

Control of a brushless motor

Abstract: A method and apparatus for controlling a brushless motor having a plurality of windings switched through a sequence of steps includes determining a transition time from one step to the next. The transition time is determined by detecting a zero crossing of a back emf in one of the plurality of windings. A delayed time to be added to the transition time is determined wherein the delayed time is selected according to the step in the sequence of steps being executed and is dependent on the duration of one of a preceding interval between zero crossings. A delay time proportional to a duration of a last shortest interval is supplied to follow a longest interval. A delay time proportional to a duration of a last longest interval is supplied to follow a shortest interval and a delay time proportional to a duration of a medium interval is supplied to follow a medium interval. The method may be used, for example, with a star or delta connected motor having any number of windings.

LDMOS implementation in a 0.35 /spl mu/m BCD technology (BCD6)

Abstract: This paper presents the integration approach followed to implement power LDMOS' up to 60 V into a 0.35 /spl mu/m process technology (BCD6) based on a CMOS plus Flash-Memory platform of equivalent lithography generation, built on a P-over P+ substrate. Experimental results on LDMOS' in terms of on-state specific resistance, off and on-state breakdown voltage, frequency behavior will be described analyzing the interactions between low voltage ULSI platform and high voltage power elements.

Importance of dynamic faults for new SRAM technologies

Abstract: New memory technologies and processes introduce new defects that cause previously unknown faults. Dynamic faults are among these new faults; they can take place in the absence of the traditional static faults. This paper describes the concept of dynamic faults, based on the fault primitive concept. It further shows, based on industrial test results, the importance of such faults for the new memory technologies, and introduces a systematic way for modeling them. It concludes that current and future SRAM products need to consider testability for dynamic faults or leave substantial DPM on the table, and it sets a direction for further research.