STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

3D stereoscopic image pairs by depth-map generation

Abstract: This work presents a new unsupervised technique aimed to generate stereoscopic views estimating depth information from a single input image. Using a single input image, vanishing lines/points are extracted using a few heuristics to generate an approximated depth map. The depth map is then used to generate stereo pairs. The overall method is well suited for real time application and works also on CFA (colour filtering array) data acquired by consumer imaging devices. Experimental results on a large dataset are reported.

Comparisons of soft error rate for SRAMs in commercial SOI and bulk below the 130-nm technology node

Abstract: This paper presents experimental ASER on SOI and BULK SRAMs for the 250-, 130-, and 90-nm technologies. The key parameters controlling soft error rate (SER) in these technologies are modeled with Monte Carlo simulations to predict SER to the 65-nm node.

A Novel Soft-Output Layered Orthogonal Lattice Detector for Multiple Antenna Communications

Abstract: This paper presents a soft-output lattice detector algorithm for multiple-input multiple-output (MIMO) communications called layered orthogonal lattice detector (LORD). LORD adopts a new lattice formulation and relies on a channel orthogonalization process. Building on the optimality of LORD for two transmit antennas this paper is a generalization of the algorithm to any number of transmit antennas. The most interesting aspect of LORD is that for two transmit antennas max-log bit soft-output information can be simply generated and for greater than two antennas approximate max-log detection is achieved with reasonable complexity. LORD can be implemented in a parallel fashion, as desirable for VLSI. Extensive simulation results in different scenarios of interest for next generation WLANs (IEEE 802.11n) are reported. The simulations show that LORD is able to achieve very high signal-to-noise ratio (SNR) gains compared to current practical soft-output MIMO detectors.

High performance extremely thin SOI (ETSOI) hybrid CMOS with Si channel NFET and strained SiGe channel PFET

Abstract: For the first time, we report high performance hybrid channel ETSOI CMOS by integrating strained SiGe-channel (cSiGe) PFET with Si-channel NFET at 22nm groundrules. We demonstrate a record high speed ring oscillator (fan-out = 3) with delay of 8.5 ps/stage and 11.2 ps/stage at V DD = 0.9V and V DD = 0.7V, respectively, outperforming state-of-the-art finFET results. A novel “STI-last” integration scheme is developed to improve cSiGe uniformity and enable ultra high performance PFET with narrow widths. Furthermore, cSiGe modulates device V t , thus providing an additional knob to enable multi-V t while maintaining undoped channels for all devices.

Nonredundant successive approximation register for A/D converters

Abstract: A successive approximation register for N bit A/D converters is presented. It code the possible 2/sup N/ conversion output values with the minimum number FF (log/sub N/). As it is nonredundant and very simple, it allows area optimisation and minor code probability error.