STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

In situ x-ray photoelectron spectroscopy analysis of SiOxFy passivation layer obtained in a SF6/O2 cryoetching process

Abstract: The oxyfluorinated silicon passivation layer created during various cryoetching processes is of interest in order to improve high aspect ratio profiles. In this work, the desorption of a SiOxFy layer obtained in an overpassivating SF6/O2 regime was investigated during the wafer warm-up from the cryogenic temperature to room temperature. An in situ x-ray photoelectron spectroscopy (XPS) device is used in order to probe the top-surface layer and understand the desorption mechanism. A new mechanism can be proposed using the evolution of fluorine, oxygen, silicon, and carbon contributions evidenced by XPS.

A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation

Abstract: Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is ${-}$ 105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply.

An Efficient Architecture for 3-D Discrete Wavelet Transform

Abstract: This paper presents an architecture of the lifting-based running 3-D discrete wavelet transform (DWT), which is a powerful image and video compression algorithm. The proposed design is one of the first lifting based complete 3-D-DWT architectures without group of pictures restriction. The new computing technique based on analysis of lifting signal flow graph minimizes the storage requirement. This architecture enjoys reduced memory referencing and related low power consumption, low latency, and high throughput compared to those of earlier reported works. The proposed architecture has been successfully implemented on Xilinx Virtex-IV series field-programmable gate array, offering a speed of 321 MHz, making it suitable for real-time compression even with large frame dimensions. Moreover, the architecture is fully scalable beyond the present coherent Daubechies filterbank (9, 7).

Resistance increase due to electromigration induced depletion under TSV

Abstract: This paper focuses on the EM induced voiding in a line ended by a TSV, and proposes an analytical model based on the link between the monitored electrical resistance increase and the matter depletion flow.

Experimental and Numerical Analysis of Hole Emission Process From Carbon-Related Traps in GaN Buffer Layers

Abstract: The role of carbon-related traps in GaN-based ungated high-electron mobility transistor structures has been investigated both experimentally and by means of numerical simulations. A clear quantitative correlation between the experimental data and numerical simulations has been obtained. The observed current decrease in the tested structure during backgating measurements has been explained simply by means of a thermally activated hole-emission process with $E_{A} = 0.9$ eV, corresponding to the distance of the acceptor-like hole-trap level from the GaN valence band. Moreover, it has been demonstrated by means of electrical measurements and numerical simulations that only a low percentage of the nominal carbon doping levels induces the observed current reduction when negative substrate bias is applied to the tested structure.