STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Grain size effects on the dielectric constant of CaCu3Ti4O12 ceramics

Abstract: The CaCu3Ti4O12 (CCTO) compound shows an unusually high and almost temperature independent dielectric constant at low frequencies. CCTO powders have been synthesized by an organic gel-assisted citrate process. The ceramic microstructure was optimized for a given sintering process. Both the grain size and density are shown to be maximum when PVA is introduced in powder before the complete formation of CCTO. A correlated increase of the dielectric constant is evidenced by impedance spectroscopy measurements. Results support the IBLC model proposed to explain the high dielectric constant of CCTO.

Poly-gate replacement through contact hole (PRETCH): a new method for high-k/metal gate and multi-oxide implementation on chip

Abstract: We report on a new concept for an easy co-integration, on a same chip, of different MOSFET configurations (GP, LP, HS, buffer transistors) realized after the end of the standard FE process. This poly-gate replacement through contact hole (PRETCH) concept enables replacement of initial poly-silicon gate and/or gate oxide by any gate stack desired. PRETCH addresses multi-Vt control, multi-oxide realization and metal gate integration challenges. As PRETCH gate replacement takes place after PMD (beginning of BE), it is perfectly suitable for high-K integration, allowing low thermal budget (no source and drain anneal seen by HK) and no particular contamination issues. Large potential of PRETCH integration is confirmed by promising morphological results and by very good electrical characteristics of both nMOS and pMOS TiN 90nm gate length MOSFETs. Integration of TiN gate with three different oxide configurations is demonstrated: initial thermal oxide left, replaced by either slot plane antenna [SPA] oxide or high-K. PRETCH concept has also been validated on 3D architectures such as DG. Finally, functional TiN DG inverters and SRAMs are demonstrated.

Method and apparatus for accessing a memory device

Abstract: A device and method for accessing a row of data in a semiconductor memory device in a single operation is disclosed. The device includes a row of latches having a width which matches the width of the memory array in the semiconductor memory device. The device includes precharge and equilibration circuitry associated with the row of latches and the row of sense amplifiers in device, and timing circuitry for controlling the operation of each in performing full page read and write operations. Writing a full row of data from the row of latches into a selected row of memory cells includes the steps of disconnecting the row of sense amplifiers from the reference voltage sources; equalizing voltage levels appearing on the bit lines of the semiconductor memory and the sense amplifiers; connecting a row of memory cells to the bit lines; driving at least one bit line of each pair of bit lines to a voltage level representing the data value stored in the corresponding latch; coupling the sense amplifiers to the reference voltage sources for powering the sense amplifiers; and disconnecting the row of memory cells from the bit lines.

Apparatus and method for synchronizing video and audio MPEG streams in a video playback device

Abstract: There is disclosed an MPEG decoder comprising: 1) a packetized elementary stream (PES) interface for receiving a plurality of packetized elementary streams associated with a single video program; 2) a presentation time stamp (PTS) detection circuit for detecting presentation time stamps in the packetized elementary streams and extracting the presentation time stamps therefrom; and 3) a selection circuit for selecting presentation time stamps associated with a first one of the plurality of packetized elementary streams and transmitting the selected presentation time stamps to a clock generation circuit, wherein the clock generation circuit generates a first reference clock signal used by a first decoder to decode the first packetized elementary stream. The clock generation circuit further generates a second reference clock signal synchronized to the first reference clock signal, wherein the second reference clock signal is used by a second decoder to decode a second packetized elementary stream in synchronization with the first packetized elementary stream.