STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Digital image stabilization by adaptive block motion vectors filtering

Abstract: This paper presents a robust algorithm for video sequence stabilization. Motion estimation is achieved using block motion vectors. In this way, the motion estimator of the MPEG encoder can be used. The simple use of block motion vectors can give unreliable global motion vectors and so elaborations are done to make the algorithm robust.

Ball-grid-array integrated circuit package with solder-connected thermal conductor

Abstract: An integrated circuit package with a path of high thermal conductivity is disclosed. The package is formed into a substrate, such as a printed circuit board or a ceramic substrate, through which an opening has been formed to receive a thermally conductive slug, formed of a material such as copper. An integrated circuit chip is mounted to one side of the slug, and the opposing surface of the slug is exposed at the underside of the substrate. The chip is wire bonded to the substrate, and is encapsulated in the conventional manner. Solder balls are attached to the underside of the substrate and of the slug in ball-grid-array fashion, for mounting to a circuit board. Upon mounting to the circuit board, a path of high thermal conductivity is provided between the chip and the circuit board, through the slug and the solder balls. According to one of the alternative disclosed embodiments, the slug extends below the surface of the substrate, and has a solder mask with larger apertures than the electrical conductors of the substrate; equivalently sized solder balls may thus be used to connect to the circuit board, to provide larger thermal conductive leads to the slug.

Fault-tolerant platforms for automotive safety-critical applications

Abstract: Fault-tolerant electronic sub-systems are becoming a standard requirement in the automotive industrial sector as electronics becomes pervasive in present cars. We address the issue of fault tolerant chip architectures for automotive applications. We begin by reviewing fault-tolerant architectures commonly used in other industrial domains where fault-tolerant electronics has been a must for a number of years, e.g., the aircraft manufacturing industrial sector. We then proceed to investigate how these architecture could be implemented on a single chip and we compare them with a metric that combines traditional terms such as cost, performance and fault coverage with flexibility, i.e. the ability of adapting to changing requirements and capturing a wide range of applications, an emerging criterion for platform design. Finally, we describe in some details a cost effective dual lock-step platform that can be used as a single fail-operational unit or as two fail-silent channels trading fault-tolerance for performance.

A Multimode Transmitter in 0.13 $\mu\hbox{m}$ CMOS Using Direct-Digital RF Modulator

Abstract: This paper presents a system-independent transmitter architecture based on a direct-digital RF-modulator which combines the D/A conversion, up-conversion, unwanted sideband rejection, power control, and part of the digital image-rejection filtering into a single mixed-signal circuit block. The multimode capability of the architecture is demonstrated with WCDMA, EDGE, and WLAN system requirements. The modulator achieves 90 dB of power control range and with an external power amplifier module, WCDMA EVM of less than 2% from signal powers of -20 dBm to +25 dBm. The noise floor level defined by the quantization noise at 190 MHz offset from the carrier is -150 dBc/Hz measured at the output of the PA with +25 dBm signal power. The analog power consumption with the maximum signal power level is 92 mW and scales down to 46 mW when reducing the signal level to -43 dBFS. The digital power consumption is 65 mW. The chip is implemented with a standard 0.13 mum 1.2 V digital CMOS with total silicon area of 4 mm2.

NBTI degradation: From transistor to SRAM arrays

Abstract: A novel composite model had been recently introduced to physically explain the mean pMOS threshold voltage shift (VTP) induced by NBTI degradation at transistor level in a quantitative way. This model is here extended to include the statistical variations introduced by intrinsic fluctuations. In a second time, the model is extrapolated up to SRAM arrays by analyzing the SRAM bitcell sensitivity to transistor degradation. This approach allows quantitative prediction of NBTI-induced VMIN variations and access time Taa degradation during burn-in operations. The key findings include (a) demonstration of non-normality of VTP shift distribution (b) NBTI contribution to product VMIN drift arises from both mean VTP drift but also from increased VTP dispersion, and (c) VTP shift non-normality is smoothed out at product level by time-zero variation of the six transistors of the SRAM bitcell.