Institution
STMicroelectronics
Company•Geneva, Switzerland•
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.
Topics: Signal, Transistor, Layer (electronics), Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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TL;DR: In this paper, the intrinsic performance of two damascene architectures is compared and the impact on electromigration of the damascenes structure is presented: due to the reverse architecture, the grain sizes and orientations are found to be linewidth dependent, and the life times extrapolated with different copper and barrier deposition processes vary on a large range: from similar to those obtained with aluminium for a full CVD metallization (barrier+copper) to more than one order of magnitude higher for a CVD barrier and a mixed CVD+PVD copper deposition
52 citations
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30 Mar 1990TL;DR: In this article, a programmable logic integrated circuit device utilizes volatile memory elements such as SRAM for retaining configuration information, and a circuit is provided as part of the device for detecting loss of power on a supply input pin.
Abstract: A programmable logic integrated circuit device utilizes volatile memory elements such as SRAM for retaining configuration information. A circuit is provided as part of the device for detecting loss of power on a supply input pin. When power loss is detected, a backup voltage supply, packaged with the programmable logic device as a unit, is connected thereto. The backup power is used to supply voltage only to those portions of the device having volatile memory elements containing configuration information. Backup power is not provided to input and output buffers of the device, thereby preventing excess loads being placed upon the backup device because of events which may occur external to the programmable logic device.
52 citations
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TL;DR: A latch-based DFE topology has been developed to overcome the classical DFE feedback loop-delay issue and an adaptive 3-tap DFE data recovery is based on a direct-feedback topology to provide a continuous equalized signal assuring a robust clock-data self alignment.
Abstract: This paper presents a 1.5 to 10 Gb/s SATA/SAS/FC receiver in 65 nm CMOS. The multiple constraints set by industry standards ask for a receiver architecture capable of simultaneously addressing channel loss impairments, high frequency-difference tracking and low serial to parallel latency. An adaptive 3-tap DFE data recovery is based on a direct-feedback topology to provide a continuous equalized signal assuring a robust clock-data self alignment. A latch-based DFE topology has been developed to overcome the classical DFE feedback loop-delay issue. A digital early-late clock recovery has been proven for plusmn5000 ppm SSC tracking. Extensive digital features allow self-calibration and internal eye analysis. The device, realized in a 65 nm technology, supports more than 36" FR4 at 6 Gb/s with SSC and 28" at 8.5 Gb/s while keeping 0.4 UI of additional sinusoidal jitter tolerance, consuming 140 mW from 1V.
52 citations
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14 Mar 2003TL;DR: In this paper, a system and method simulates a universal serial bus (USB) smart card device connected to a USB host device for development and debugging and includes a computer simulator and USB host devices with host controller operatively connected along a communications link with the computer simulator for transmitting or receiving data packets to or from the simulator.
Abstract: A system and method simulates a universal serial bus (USB) smart card device connected to a USB host device for development and debugging and includes a computer simulator and USB host device with host controller operatively connected along a communications link with the computer simulator for transmitting or receiving data packets to or from the computer simulator. A microcontroller is located between the computer simulator and USB host device and translates the data packets into a USB protocol to be used by the USB host device and defined by the computer simulator.
52 citations
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20 Sep 1988TL;DR: In this article, a chip type memory card is inserted into a terminal of a reserving device, which makes the reservation by sending indications about this reservation to a terminal located near the goods or services to be delivered.
Abstract: To reserve a supply of a good or service, a chip type memory card is inserted into a terminal of a reserving device. This reserving device makes the reservation by sending indications about this reservation to a terminal located near the goods or services to be delivered. On the agreed date and at the agreed place, the renting party goes to this terminal and inserts his memory card therein. The terminal then tells him where and how he should get and use the service or good reserved by him. This system can be applied in particular when the good or service to be obtained by self-service concerns the renting of a vehicle.
52 citations
Authors
Showing all 17185 results
Name | H-index | Papers | Citations |
---|---|---|---|
Bharat Bhushan | 116 | 1276 | 62506 |
Albert Polman | 97 | 445 | 42985 |
G. Pessina | 84 | 828 | 30807 |
Andrea Santangelo | 83 | 886 | 29019 |
Paolo Mattavelli | 74 | 482 | 19926 |
Daniele Ielmini | 68 | 367 | 16443 |
Jean-François Carpentier | 62 | 459 | 14271 |
Robert Henderson | 58 | 440 | 13189 |
Bruce B. Doris | 56 | 604 | 12366 |
Renato Longhi | 55 | 177 | 8644 |
Aldo Romani | 54 | 425 | 11513 |
Paul Muralt | 54 | 344 | 12694 |
Enrico Zanoni | 53 | 705 | 13926 |
Gaudenzio Meneghesso | 51 | 703 | 12567 |
Franco Zappa | 50 | 274 | 9211 |