STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

FlexWare : A Flexible Firmware Development Environment for Embedded Systems

Abstract: The Flexware system is a software/firmware development environment for application specific instruction set processors (ASIPs) and commercial processors. It is currently composed of two main tools : 1. An instruction set simulator, INSULIN, which provides a cycle true VHDL based simulation environment for a user defined instruction set. The use of INSULIN has allowed to model in-house (two DSPs and one microcontrol ASIP) and commercial processors (e.g. the Intel 80C196 and SGS-Thomson ST7291 microcontrollers, as well as the SGS-Thomson ST18950 DSP) in a fraction of the time required for a manually developed model. Execution times are in the order of thousands of instructions per second on a Sparc 2. 2. A retargetable code generator, CODESYN, which takes one or more algorithms expressed in a high-level language and maps them onto a user defined instruction set to produce optimized machine code for a target ASIP or a commercial processor core. The development of a CODESYN based compiler for a DSP ASIP produced results within 20% of hand coded assembler.

Recent developments in high integration multi-standard CMOS transceivers for personal communication systems

Abstract: Issues associated with the integration of transceiver components on to a single silicon substrate are discussed. In particular, recently proposed receiver and transmitter architectures for high integration are examined on the promise of providing multistandard capability. In addition, existing barriers to lower power transceiver operation are examined as well as some proposed directions for future integrated transceiver research and development.

Capacitive boosting circuit for the regulation of the word line reading voltage in non-volatile memories

Abstract: A circuit for the regulation of the word line voltage in a memory, comprising a voltage regulator suitable to generate an output regulated voltage to be supplied to one or more word lines of the memory when the one or more word lines are being selected. The circuit includes a voltage boosting circuit that is coupled to the output of said voltage regulator and that can be activated upon the selection of one or more memory word lines in order to boost the regulated voltage upon the selection of the one or more memory word lines.

Still picture format for subsequent picture stitching for forming a panoramic image

Abstract: A method for storing a plurality of still images to form a panoramic image. The method comprising the steps of receiving a first image forming a part of a series of images to form a panoramic image and storing the first image in memory. When one or more subsequent images after the first image are received the steps of calculating one or more panoramic parameters between a current image and a previous image stored in memory and storing the current image with the one or more panoramic parameters in memory are performed.

Method of manufacturing an integrated edge structure for high voltage semiconductor devices, and related integrated edge structure

Abstract: Method of manufacturing an edge structure for a high voltage semiconductor device, including a first step of forming a first semiconductor layer of a first conductivity type, a second step of forming a first mask over the top surface of the first semiconductor layer, a third step of removing portions of the first mask in order to form at least one opening in it, a fourth step of introducing dopant of a second conductivity type in the first semiconductor layer through the at least one opening, a fifth step of completely removing the first mask and of forming a second semiconductor layer of the first conductivity type over the first semiconductor layer, a sixth step of diffusing the dopant implanted in the first semiconductor layer in order to form a doped region of the second conductivity type in the first and second semiconductor layers. The second step up to the sixth step are repeated at least one time in order to form a final edge structure including a number of superimposed semiconductor layers of the first conductivity type and at least two columns of doped regions of the second conductivity type, the columns being inserted in the number of superimposed semiconductor layers and formed by superimposition of the doped regions subsequently implanted through the mask openings, the column near the high voltage semiconductor device being deeper than the column farther from the high voltage semiconductor device.