STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Method and system for providing an electronic program guide

Abstract: In a method for providing a program guide in a program receiver, program schedule data is received, wherein the program schedule data associates programs with time slots on a particular channel of a plurality of channels. For a first time slot of a virtual channel, and using the program schedule data, a first program is selected from a first channel available for reception in a first selected time slot. For a second time slot of the virtual channel, a second program is selected from a second channel available for reception in a second selected time slot. In response to a request to display a schedule of programs, a schedule of the virtual channel is displayed, including the first and second programs scheduled respectively in the first and second time slots of the virtual channel.

High-capacitance photodiode

Abstract: A monolithic photodetector including a photodiode, a precharge MOS transistor, a control MOS transistor, a read MOS transistor, and a transfer MOS transistor, the photodiode and the transfer transistor being formed in a same substrate of a first conductivity type, the photodiode including a first region of the second conductivity type formed under a second region of the first conductivity type more heavily doped than the first region, and above a third region of the first conductivity type more heavily doped than the substrate, the first region being the source of the second conductivity type of the transfer transistor, the second and third regions being connected to the substrate and being at a fixed voltage.

A 3MHz Bandwidth Low Noise RF All Digital PLL with 12ps Resolution Time to Digital Converter

Abstract: A high performance all digital PLL RF synthesizer is presented. The key building block is a high resolution time to digital converter (TDC) that allows for low in-band phase noise. The TDC uses a novel architecture that combines a simple analog circuitry with a digital control loop to achieve a PVT stable sub-gate delay quantization step, with small area and low power consumption. A prototype of the TDC integrated in 0.13mum CMOS shows 12ps resolution with 1 and 1.15 LSB of DNL and INL respectively. A complete 2GHz ADPLL test chip has been then integrated and measured showing an in-band phase noise of -102dBc and maximum in-band spurs of -42dBc while consuming 15mW

Method of estimating fading coefficients of channels and of receiving symbols and relative single or multi-antenna receiver and transmitter

Abstract: The method is for estimating the fading coefficients of a plurality of transmission channels on which signals to be sent, generated as a function of a sequence of symbols, are transmitted according to a particular modulation, e.g. AM-PSK modulation. The fading coefficients are estimated by using estimations of the transmitted symbols obtained in advance, thus obtaining DC components of the received signal by coherent demodulation locked to the phases of the transmitted AM-PSK signals, and processing these DC components. The method may not require the choice of a stochastic distribution model of the channel fading, thus it remains efficient even when the channel characteristics vary significantly. Moreover, the method works correctly even if the received stream is disturbed by inter-symbolic interference (ISI) and/or by multi-path fading.

Mixed technology integrated device comprising complementary LDMOS power transistors, CMOS and vertical PNP integrated structures having an enhanced ability to withstand a relatively high supply voltage

Abstract: Complementary LDMOS and MOS structures and vertical PNP transistors capable of withstanding a relatively high voltage may be realized in a mixed-technology integrated circuit of the so-called "smart power" type, by forming a phosphorus doped n-region of a similar diffusion profile, respectively in: the drain zone of the n-channel LDMOS transistors, in the body zone of the p-channel LDMOS transistors forming first CMOS structures; in the drain zone of n-channel MOS transistors belonging to second CMOS structures and in a base region near the emitter region of isolated collector, vertical PNP transistors, thus simultaneously achieving the result of increasing the voltage withstanding ability of all these monolithically integrated structures. The complementary LDMOS structures may be used either as power structures having a reduced conduction resistance or may be used for realizing CMOS stages capable of operating at a relatively high voltage (of about 20V) thus permitting a direct interfacing with VDMOS power devices without requiring any "level shifting" stages. The whole integrated circuit has less interfacing problems and improved electrical and reliability characteristics.