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Institution

STMicroelectronics

CompanyGeneva, Switzerland
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.


Papers
More filters
Patent
22 Feb 2007
TL;DR: In this paper, a ripple compensator for a switching converter of the type includes a switching means and filtering means comprises means for injecting a compensating current such that the AC component of the switching current and the compensating currents are in opposite phases.
Abstract: Systems and methods for compensating ripple current and improved ripple compensators and switching converters capable of compensating ripple current. In one embodiment, the ripple compensator for a switching converter of the type includes a switching means and filtering means comprises means for injecting a compensating current such that the AC component of the switching current and the compensating current are in opposite phase. In addition, the compensation current is elaborated from a signal at a node between the switching means and the filtering means.

85 citations

Patent
20 Sep 1996
TL;DR: In this article, a voltage regulator with load pole stabilization is disclosed, which consists of an error amplifier, an integrator which includes a switched capacitor, a pass transistor, and a feedback circuit.
Abstract: A voltage regulator with load pole stabilization is disclosed. The voltage regulator consists of an error amplifier, an integrator which includes a switched capacitor, a pass transistor, and a feedback circuit. In one embodiment, the integrator circuit includes an amplifier, a capacitor, and a switched capacitor which is driven by a voltage controlled oscillator. The voltage controlled oscillator changes its frequency of oscillation proportional to the output current. In another embodiment, the switched capacitor is driven by a current controlled oscillator whose frequency of oscillation is also proportional to the output current of the voltage regulator. When the output current demand is large, the controlled oscillators increase the frequency which decreases the effective resistance of the switched capacitor thereby changing the frequency of the zero to respond to the change in the load pole. Conversely, the effective resistance is increased as the current demand is decreased, also to respond to the decrease in load pole. The controlled oscillator may be coupled to a current sensing device that generates a scaled version of the load current and couples to the regulated voltage output. The controlled oscillator is restricted to operating voltages that are related to the regulated output voltage and a control current that is a scaled version of the load current. Consequently, the disclosed voltage regulator has high stability without consuming excess power.

84 citations

Journal ArticleDOI
27 Nov 2007
TL;DR: Continuous frequency tuning by control of the magnetic field of a transformer - capacitor tank, in a selective oscillator, is explored in this work, and oscillation amplitude, frequency tuning band, phase noise, and phase accuracy are analyzed.
Abstract: Continuous frequency tuning by control of the magnetic field of a transformer - capacitor tank, in a selective oscillator, is explored in this work. A quadrature generator is built connecting two identical transformer - capacitor oscillator cells in a feedback loop. The topology itself assures the currents in the transformer windings are aligned in phase, while their relative amplitude determines, via magnetic coupling, oscillators' tank reactance, i.e., oscillation frequency. This paper introduces the idea, analyzes oscillation amplitude, frequency tuning band, phase noise, and phase accuracy, and discusses design and experiments. Prototypes, realized in 65 nm CMOS, employing MOS varactors to further extend operation bandwidth, show the following performances: 3.2 GHz and 7.3 GHz minimum and maximum oscillation frequency, respectively. Phase noise figure of merit of 176.5 dB at 3.2 GHz and 170.5 dB at 6.4 GHz is observed, with 24 mW maximum power consumption and 1.5 maximum deviation from quadrature.

84 citations

Patent
22 Sep 2005
TL;DR: In this paper, a parallel deblocking filtering method was proposed for removing edge artifacts created during video compression, which includes loading luma samples for a macroblock and filtering a set of horizontal edges of the macroblock.
Abstract: A parallel deblocking filtering method, and deblocking filter processor performing such deblocking, for removing edge artifacts created during video compression. The method includes loading luma samples for a macroblock. Filtering is performed on a set of vertical edges of the macroblock using information in the luma samples, with vertical edge filtering occurring concurrently with the loading of the luma samples. The method also includes filtering a set of horizontal edges of the macroblock using information in the luma samples. The horizontal edge filtering occurs in parallel with vertical edge sampling and with loading operations. The use of parallel and concurrent operations significantly enhances the efficiency of the deblocking method. Storing of filtered samples is also performed in the method, and this storing is performed concurrently with some loading operations as well as filtering operations. Edge filtering includes performing filtering to the H.264 standard and its deblocking filtering algorithm.

84 citations

Journal ArticleDOI
TL;DR: In this paper, the coupling of the lateral, front and back interfaces is analyzed based on experimental results in FinFETs with various geometries and the transport properties at each interface are presented and compared.
Abstract: Double-gate devices are best candidates for the MOSFET scaling down to the deca-nanometer range. The motivation of this work is to investigate the coupling effects in FinFETs and to extract the carrier mobility in each of the four possible channels. The coupling of the lateral, front and back interfaces is analyzed based on experimental results in FinFETs with various geometries. The influence of the substrate bias on the front and lateral surface potentials is especially emphasized. The back-gate action is minimized in ultra-narrow fins. Finally, the transport properties at each interface are presented and compared. The electron and hole mobilities are significantly lower on the fin edges than at the top and bottom interfaces.

84 citations


Authors

Showing all 17185 results

NameH-indexPapersCitations
Bharat Bhushan116127662506
Albert Polman9744542985
G. Pessina8482830807
Andrea Santangelo8388629019
Paolo Mattavelli7448219926
Daniele Ielmini6836716443
Jean-François Carpentier6245914271
Robert Henderson5844013189
Bruce B. Doris5660412366
Renato Longhi551778644
Aldo Romani5442511513
Paul Muralt5434412694
Enrico Zanoni5370513926
Gaudenzio Meneghesso5170312567
Franco Zappa502749211
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
202225
2021560
2020798
2019952
2018948
2017781