STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Multi-scale Analysis of MEMS Sensors Subject to Drop Impacts

Abstract: The effect of accidental drops on MEMS sensors are examined within the frame-work of a multi-scale finite element approach. With specific reference to a polysilicon MEMSaccelerometer supported by a naked die, the analysis is decoupled into macro-scale (at dielength-scale) and meso-scale (at MEMS length-scale) simulations, accounting for the verysmall inertial contribution of the sensor to the overall dynamics of the device. Macro-scaleanalyses are adopted to get insights into the link between shock waves caused by the impactagainst a target surface and propagating inside the die, and the displacement/acceleration his-tories at the MEMS anchor points. Meso-scale analyses are adopted to detect the most stresseddetails of the sensor and to assess whether the impact can lead to possible localized failures.Numerical results show that the acceleration at sensor anchors cannot be considered an ob-jective indicator for drop severity. Instead, accurate analyses at sensor level are necessary toestablish how MEMS can fail because of drops.

Circuit connection in an electrical assembly

Abstract: An electrical assembly comprises an electrical component 11 having an array of contact bumps 18. The component 11 is mounted on a multilayer printed circuit board 12 having a plurality of conducting pins 28 located in holes in the board 12 and having pointed ends 29 projecting above the board and making electrical contact with the bumps 18 on the component 11.

An integrated gate field-effect transistor with gate-drain overlap and method of making the same

Abstract: A method of forming an insulated-gate field-effect transistor, and the transistor formed thereby, is described. According to a first embodiment, an Inverted-T gate structure is formed by the deposition of a polycrystalline silicon layer, followed by the deposition of a metal silicide layer thereover. The metal silicide layer is etched with etchant which does not significantly etch polysilicon, to define the upper portion of the gate electrode. The reachthrough lightly-doped source/drain extensions are then implanted through the polysilicon layer, using the upper gate electrode portion as a mask. Sidewall spacers are formed on the sides of the upper portion of the gate electrode, and the polysilicon etched using the spacers as a mask, to define the inverted-T gate structure. In addition, either with the inverted-T gate structure or in conjunction with conventional gate structures, a method is disclosed which uses a first sidewall film to define the location of the source/drain implant relative to the LDD regions, and a second sidewall spacer to space direct react silicide formation from the gate, so that the dimensions of the graded junction may be defined independently from that of the silicidation reaction.

A statistical model for SILC in flash memories

Abstract: The reliability of flash memories is strongly. limited by the stress-induced leakage current (SILC), which leads to accelerated charge-loss phenomena in a few anomalous cells. Estimating the reliability of large flash arrays requires that physically-based models for the statistical distribution of SILC are developed. In this paper, we show a physical model for the leakage mechanism in thin oxides, which is able us to explain the anomalous leakage-conduction in tail cells. The physical model is then used for a quantitative evaluation of the SILC distribution in large flash arrays. The new model can reproduce the statistics of SILC for a wide range of tunnel-oxide thickness, and can provide a straightforward estimation of the reliability for large flash arrays.

Semiconductor device package with dies mounted on both sides of the central pad of a metal frame

Abstract: A semiconductor device in a plastic or ceramic package contains at least one silicon die on each side of a central die pad of a single metal frame, thus allowing a substantial space saving on the printed circuit assembly card. The bonding of the silicon dies and the soldering of the connecting wires are performed on both sides of the frame by emplying a special slotted clamp fixture inside which a strip of frames is clamped during these assembly operations and relative quality control operations.