STMicroelectronics

About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.

Solid state fingerprint sensor packaging apparatus and method

Abstract: A planar, capacitive-type, rectangular, and multi-pixel fingerprint sensing array is mounted on the horizontal and generally rectangular top-surface of a dome that extends upward generally from the center of a horizontally disposed and generally rectangular silicon substrate member. The dome is formed by four upward extending and inclined, or tapered, side wall surfaces, at least one wall surface of which carries electrical circuit paths that electrically connected to the various circuit elements of the sensing array. A generally rectangular, encircling and wall-like card carrier assembly includes a generally horizontal upper-surface having a generally centered opening through which only the dome and sensing array project upward. The bottom-surface of the card carrier assembly is mounted to edge portions of the silicon substrate member in a manner to surround and protect all but the upward extending dome. A flexible membrane or laminate is sealed to the top-surface of the card carrier assembly to form a flexible surface over the sensing array. The card carrier assembly includes a circuit path having an external portion and having an internal portion that connects to the wall-mounted internal electrical circuit paths, the external portion providing external connection to the internal sensing array.

SET and RESET pulse characterization in BJT-selected phase-change memories

Abstract: This paper presents program pulse characterization in an 8-Mb BJT-selected phase-change memory test chip. Experimental results of the impact of the bit-line resistance over programming pulse efficiency are provided. Furthermore, in order to compensate for spreads in cell physical parameters in an array portion, a non-conventional staircase-down program pulse is proposed and experimentally evaluated.

Digital phase lock loop

Abstract: A system includes a digital phase lock loop (PLL) constructed from an all digital circuit implementation and standard cell construction. The digital PLL includes a digital frequency synthesizer and a digital phase detector. The digital frequency synthesizer includes a digital DLL including a plurality of delay chains, each of the delay chains including at least one digitally programmable delay element for configuring the plurality of delay chains to achieve a phase lock with an input reference signal. The digital frequency synthesizer also a non-glitching MUX electrically coupled to the digital DLL for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse glitch-free from the selected output tap, and a phase accumulator electrically coupled to the non-glitching MUX for precisely dividing a timing period of the input reference signal and for selecting a tap output from one of the at least one digitally programmable delay element to select at least one pulse at a precise point in the timing period from the output tap. The digital phase detector, is electrically coupled to the digital frequency synthesizer to compare an edge of the input reference signal to an edge of a synthesized signal to provide a digital code information representing a phase error between the edge of the input reference signal and the edge of the synthesized signal.

Static and dynamic behavior of paralleled IGBTs

Abstract: Problems associated with power device characteristics when power devices are connected in parallel, such as thermal stability and balanced switching behavior, can be solved by using insulated gate bipolar transistors (IGBTs). The author deals with parallel IGBT behaviors analyzing both static and dynamic characteristics. The influence of heatsink mounting, layout, and drive circuit are described in order to demonstrate the best way to make IGBTs parallel for optimum performance. In addition, the major advantages of the ISOTOP package are shown. >

Extended Dynamic Range From a Combined Linear-Logarithmic CMOS Image Sensor

Abstract: A CMOS image sensor that can operate in both linear and logarithmic mode is described. Two sets of data are acquired and combined in the readout path to render a high dynamic range image. This is accomplished in real-time without the use of frame memory. A dynamic range in excess of 120 dB was achieved at 26 frames/s (352times288-array). The system addresses the problems of high fixed pattern noise (FPN), slow response time, and low signal-to-noise ratio (SNR) in logarithmic mode. FPN has been effectively reduced by single and two parameter calibration, the latter achieving FPN of 2% per decade. A novel on-chip method of deriving a reference point has been implemented. The system is fabricated in a 0.18-mum 1P4M process and achieves a pixel pitch of 5.6 mum with 7 transistors per pixel