Institution
STMicroelectronics
Company•Geneva, Switzerland•
About: STMicroelectronics is a company organization based out in Geneva, Switzerland. It is known for research contribution in the topics: Signal & Transistor. The organization has 17172 authors who have published 29543 publications receiving 300766 citations. The organization is also known as: SGS-Thomson & STM.
Topics: Signal, Transistor, Layer (electronics), Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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30 Sep 1998
TL;DR: In this article, a look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the memory for an additional data burst, which is transferred through the direct memory access unit to the FifO memory when the lookahead water-mark flag indicates that sufficient space is available.
Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.
61 citations
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30 Dec 1994TL;DR: In this paper, a high-side gate driving circuit with a differential error amplifier is proposed, where a current path is provided from the gate to the source of the power device, and a constant current is provided to the gate.
Abstract: A high-side gate driving circuit, where a current-mode differential error amplifier is used to regulate the current sourced to the gate. A current path is provided from the gate to the source of the power device, and a constant current is provided to the gate. A variable current source is also provided, and this current source is controlled by the output of the error amplifier. Preferably a voltage offset (avalanche breakdown diode) is interposed between the gate and source of the high-side driver; this ensures that the feedback loop will operate in a bistable mode, which avoids instability problems.
60 citations
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16 Mar 2004TL;DR: In this paper, a method of processing video frame data includes the steps of: receiving a video frame, partially decoding the video frame; fully decoding and encoding the macroblocks based on the determined video data parameters to provide a compressed video frame for subsequent display.
Abstract: A method of processing video frame data includes the steps of: receiving a video frame; partially decoding the video frame; fully decoding the video frame to produce macroblocks; determining video data parameters from the partially decoded video frame or both the partially and fully decoded video frame; and encoding the macroblocks based on the determined video data parameters to provide a compressed video frame for subsequent display.
60 citations
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TL;DR: In this article, the impact of the morphology of p-type implanted SiC, annealed under different conditions, on the properties of Ti/Al contacts and the influence of different annealing conditions on the channel mobility in 4H-SiC MOSFETs was also addressed.
60 citations
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04 Dec 1998TL;DR: In this article, the L1 tag RAM is placed before the L2 data RAM for both CPU write transactions and L1 line-fill transactions, such that a line is in the L 1 cache before updating it.
Abstract: A cache subsystem in a data processing system is structured to place the L1 cache RAMs after the L2 cache RAMs in the pipeline for processing both CPU write transactions and L1 line-fill transactions. In this manner the lines loaded into the L1 cache are updated by all CPU write transactions without having to perform any explicit checks. The present invention also places the L1 tag RAM before the L1 data RAM for both CPU write transactions and L1 line-fill transactions, such that CPU write transactions may check that a line is in the L1 cache before updating it. L1 line-fill transactions can then check that the line to be transferred from the L2 cache to the L1 cache is not already in the L1 cache.
60 citations
Authors
Showing all 17185 results
Name | H-index | Papers | Citations |
---|---|---|---|
Bharat Bhushan | 116 | 1276 | 62506 |
Albert Polman | 97 | 445 | 42985 |
G. Pessina | 84 | 828 | 30807 |
Andrea Santangelo | 83 | 886 | 29019 |
Paolo Mattavelli | 74 | 482 | 19926 |
Daniele Ielmini | 68 | 367 | 16443 |
Jean-François Carpentier | 62 | 459 | 14271 |
Robert Henderson | 58 | 440 | 13189 |
Bruce B. Doris | 56 | 604 | 12366 |
Renato Longhi | 55 | 177 | 8644 |
Aldo Romani | 54 | 425 | 11513 |
Paul Muralt | 54 | 344 | 12694 |
Enrico Zanoni | 53 | 705 | 13926 |
Gaudenzio Meneghesso | 51 | 703 | 12567 |
Franco Zappa | 50 | 274 | 9211 |