Institution
Freescale Semiconductor
About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..
Topics: Layer (electronics), Signal, Transistor, Integrated circuit, Voltage
Papers published on a yearly basis
Papers
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01 Sep 2006TL;DR: In this article, the authors present advanced TLP measurement techniques down to 1.2ns pulses and compare gated, STI and abutted tie diodes and introduce a compact model with a new thermal equivalent circuit fitting data in the entire CDM to HBM timeframe.
Abstract: We present advanced TLP measurement techniques down to 1.2ns pulses. We compare gated, STI and abutted tie diodes and introduce a compact model with a new thermal equivalent circuit fitting data in the entire CDM to HBM timeframe. Further, we compare diode area efficiency in a full ESD protection network.
51 citations
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08 May 2003TL;DR: In this paper, the first and second amplifier transistors have a common element thereof electrically interconnected with a common bus, each leg having a distal end proximate one of the transistors.
Abstract: A radio frequency power amplifier has first and second amplifier transistors. The first and second amplifier transistors have a common element thereof electrically interconnected with a common bus. A forked conductor having two legs thereof electrically connected to the common bus, each leg having a distal end proximate one of the first and second amplifier transistors. The common bus and the forked conductor are generally symmetric about an axis about which the first and second amplifier transistors are symmetrically disposed.
51 citations
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20 Jun 1994TL;DR: In this paper, a logic circuit including a pair of FETs connected in parallel and including first and second common current terminals, each FET having a control terminal connected to receive a logic signal thereon, is presented.
Abstract: A logic circuit including a pair of FETs connected in parallel and including first and second common current terminals, each of the FETs further having a control terminal connected to receive a logic signal thereon. A negative differential resistance device affixed to one of the first and second common current terminals and having a conductance characteristic such that the device operates at a peak current when one of the FETs is turned ON and at a valley current when both of the FETs are simultaneously turned ON. A load resistance coupled to the other of the first and second common current terminals and providing an output for the logic circuit.
51 citations
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09 May 2006TL;DR: In this paper, a method for operating a transceiver that comprises: transmitting a preamble (905), transmitting an outer header (320) identifying parameters of an outer payload (340), after transmitting the preambles, and transmitting the outer payload after transmitting an inner header (345) (920), and repeating the transmitting of the inner header and the inner payload a plurality of times.
Abstract: A method (900) is provided for operating a transceiver that comprises: transmitting a preamble (905); transmitting an outer header (320) identifying parameters of an outer payload (340), after transmitting the preamble (910); and transmitting the outer payload after transmitting the outer header. The transmitting of the outer payload includes: transmitting an inner header (325) identifying parameters of an inner payload (345) (920); transmitting an inner payload after transmitting the inner header (930); and repeating the transmitting of the inner header and the transmitting of the inner payload a plurality of times. A corresponding method of operating a receiver functions by receiving each of these transmitted elements.
51 citations
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10 Mar 2006TL;DR: In this paper, a method and apparatus for encapsulating electronic devices, comprising of one or more electronic devices with primary faces (62) having electrical contacts (69), opposed rear faces (65) and edges (64) there between, is provided.
Abstract: Methods and apparatus are provided for encapsulating electronic devices, comprising: providing one or more electronic devices (62) with primary faces (63) having electrical contacts (69), opposed rear faces (65) and edges (64) therebetween. A sacrificial layer (70) is provided on the primary faces (63). The devices (62) are mounted on a temporary support (80) so that the sacrificial layer (70) faces toward the temporary support (80). A plastic encapsulation (86)is formed in contact with at least the lateral edges (64) of the electronic devices (62). The plastic encapsulation (86) is at least partially cured and the devices (62) and plastic encapsulation (86) separated from the temporary support (80), thereby exposing the sacrificial layer (70). The sacrificial layer (70) is removed. The devices (62) and edge-contacting encapsulation are mounted on a carrier (90) with the primary faces (63) and electrical contacts (69) exposed and, optionally, further cured. Insulators (94) and conductors (96) applied to the primary faces couple electrical contacts (69) on various devices (62) to each other and to external contacts, thereby forming an integrated multi-device panel (88″).
51 citations
Authors
Showing all 7673 results
Name | H-index | Papers | Citations |
---|---|---|---|
David Blaauw | 87 | 750 | 29855 |
Krishnendu Chakrabarty | 79 | 996 | 27583 |
Rajesh Gupta | 78 | 936 | 24158 |
Philippe Renaud | 77 | 773 | 26868 |
Min Zhao | 71 | 547 | 24549 |
Gary L. Miller | 63 | 306 | 13010 |
Paul S. Ho | 60 | 475 | 13444 |
Ravi Subrahmanyan | 59 | 353 | 14244 |
Jing Shi | 53 | 222 | 10098 |
A. Alec Talin | 52 | 311 | 12981 |
Chi Hou Chan | 48 | 511 | 9504 |
Lin Shao | 48 | 380 | 12737 |
Johan Åkerman | 48 | 306 | 9814 |
Philip J. Tobin | 47 | 186 | 6502 |
Alexander A. Demkov | 47 | 331 | 7926 |