Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Z-axis accelerometer with at least two gap sizes and travel stops disposed outside an active capacitor area

Abstract: An accelerometer includes a pair of conductive plates fixedly mounted on a substrate surface, a structure coupled to the substrate surface and suspended above the conductive plates, and at least one protective shield mounted on the substrate surface. The structure includes two regions of differing total moments disposed above a respective conductive plate and separated by a flexure axis about which the structure rotates during an acceleration normal to the substrate, each region having a substantially planar outer surface and an inner surface having a first corrugation formed thereon. For each of the two regions, an inner gap exists between the first corrugation and an opposing conductive plate, and an outer gap exists between the substantially planar outer surface and the opposing conductive plate, the outer gap being larger than the inner gap. The at least one protective shield is placed apart from either of the conductive plates.

Vertically stacked vertical transistors used to form vertical logic gate structures

Abstract: A transistor (10) has a substrate (12) and a diffusion (14). A gate conductive layer (18) overlies the substrate (12) and has a sidewall formed by an opening that exposes the substrate (12). A sidewall dielectric layer (22) formed laterally adjacent the conductive layer (18) sidewall functions as a gate dielectric for the transistor (10). A conductive region is formed within the opening. The conductive region has a first current electrode region (28) and a second control electrode region (34) and a channel region (30) laterally adjacent the sidewall dielectric layer (22). A plurality of transistors, each in accordance with transistor (10), can be stacked in a vertical manner to form logic gates such as NMOS or PMOS NAND, NOR, and inverter gates, and/or CMOS NAND, NOR, and inverter gates with one or more inputs.

Method for allocating data in a data communication system

Abstract: A communications system (30) includes a transceiver (42) for transmitting data from a plurality of bins. Specifically, the BER of the bins is substantially equalized by allocating data by determining a projected margin. The projected margin is calculated for each bin by subtracting a reference signal-to-noise value from an estimated bin signal-to-noise value. The reference signal-to-noise value is predetermined by theoretical calculation or empirical data and stored in a look-up table. Bits are allocated to the bin having the maximum projected margin. This provides the best BER without changing the transmit power.

Process for fabricating a semiconductor device having a high reliability dielectric material

Abstract: A process for fabricating a high-reliability composite dielectric layer (19) includes the formation of a first oxynitride layer (14) on the surface (12) of a silicon substrate (10). The formation of the first oxynitride layer (14) is followed by an oxidation step to form a silicon dioxide layer (16) at the surface (12) of the substrate (10) and underlying the first oxynitride layer (14). The composite dielectric layer (19) is completed by exposing the substrate (10) to nitrous oxide, and diffusing a nitrogen bearing species through both the silicon dioxide layer (16) and the first oxynitride layer (14) to form a second oxynitride layer (18) underlying the silicon dioxide layer (16). The composite dielectric layer (19) exhibits a nitrogen-rich region at the interface between second oxynitride layer (18) and the silicon substrate (10). A second nitrogen rich region is also formed near the surface of the first oxynitride layer (14).

Digital color image pre-processing

Abstract: In one embodiment, the invention involves a method for processing an image. A sensor output is provided. An automatic gain control of the sensor output is performed to generate a first output. An automatic white balance correction to the first output is performed to generate a second output. A gamma correction of the second output is performed to generate a third output. A color interpolation is performed to the third output to generate a fourth output. A low-pass spatial filtration of the fourth output is performed to generate a fifth output. A color saturation and correction of the fifth output is performed to generate a sixth output, and a high-pass spatial filtration of the sixth output is performed to generate an image output.