Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Receiver with automatic gain control that operates with multiple protocols and method thereof

Abstract: An automatic gain control (AGC) method and circuit ( 10 ) within a receiver uses a digital state machine ( 26 ) to implement the AGC function. independent from interaction with a host processor ( 36 ) and for multiple modulation protocols without duplicating circuitry. Modulation protocol and parameters for any of various gain responses are stored in a register ( 29 ). Multiple states, each corresponding to a predetermined range of RF input signal strength, are stored in the register. Each state contains parameters that determine a gain control signal for controlling a variable gain amplifier ( 16 ). The states are independent and may be selectively disabled to create asymmetric responses. Within any state, an adaptable number of iterations may be set to implement a different update rate or step size after a predetermined number of closed loop gain change iterations has not resulted in a transition to a state that represents a desired output gain.

Bit-wise conditional write method and system for an MRAM

Abstract: A bit-wise conditional write method and apparatus to minimize power consumption in integrated circuit (IC) magnetoresistive random access memory (MRAM) systems. In a first embodiment, the current logic state of each data bit of a word stored in the MRAM is compared to a corresponding input bit and only those stored data bits which are different are written. In a second embodiment, for each stored data bit which is not being written, the current logic state is guarded against inadvertent modification when other data bits of the word are written. In a third embodiment, if the logic states of a majority of the stored data bits comprising a word are different from the logic states of the respective input bits, the input bits are first complemented so that less than a majority of the stored data bits actually need to be changed, and a complement bit, appended to each word in the MRAM, is set to indicate that the correct logic states of the stored data bits comprising the respective word must be restored upon subsequent readout.

Highly Manufacturable 45nm LSTP CMOSFETs Using Novel Dual High-k and Dual Metal Gate CMOS Integration

Abstract: This paper reports the first demonstration of dual high-k and dual metal gate (DHDMG) CMOSFETs meeting the device targets of 45nm low stand-by power (LSTP) node. This novel scheme has several advantages over the previously reported dual metal gate integration, enabling the high-k and metal gate processes to be optimized separately for N and PMOSFETs in order to maximize performance gain and process controllability. The proposed gate stack integration results in a symmetric short channel Vt of ~plusmn0.45V with >80% high field mobility for both N and PMOSFETs and significantly lower gate leakage compared to poly/SiON stack

Integrated vertical stack capacitor

Abstract: An integrated circuit capacitor ( 60 ) uses multiple electrically conductive stacks ( 63-68, 70 ) to optimize capacitance density. A second stack ( 70 ) is a first nearest neighbor to a first stack ( 66 ). A third stack ( 65 ) is a second nearest neighbor to the first stack. Each of the three stacks defines vertices of an isosceles triangle ( 20 ) formed in a plane substantially perpendicular to the three stacks. The isosceles triangle does not have a ninety degree angle. The isosceles triangle may also be implemented as an equilateral triangle.

Method of packaging an integrated circuit die

Abstract: A structure (40) for holding an integrated circuit die (38) during packaging includes a support substrate (42), a release film (44) attached to the substrate (42), and a swelling agent (60). A method (34) of packaging the die (38) includes placing the die (38) on the substrate (42) with its active surface (52) and bond pads (54) in contact with the film (44). The agent (60) is applied over an adhesive coating (50) of the film (44). The agent (60) causes the adhesive (50) to swell into contact with the bond pads (54) and/or to form fillets (64) of adhesive (50) about the die (38). The die (38) is encapsulated in a molding material (72) and released from the substrate (42) as a panel (74) of dies (38). Swelling of the adhesive (50) about the bond pads (54) prevents the molding material (72) from bleeding onto the bond pads (54).