Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method of cell characterization in a distributed simulation system

Abstract: A method executed by a computer program performs cell characterization in a distributed simulation system by partitioning characterization tasks into individual simulations. A simulation job is generated based on the individual simulations and placed into a simulation job queue. The simulation job queue is copied into a database. The simulation job is accessed and processed in a remote simulator. The remote simulator returns a simulation status and simulation results which are placed into an acknowledge queue. The simulation process is repeated upon detecting an error condition from the simulation status. The simulation status is read from the acknowledge queue and the acknowledge queue is copied into the database.

Sense amplifier for a memory having at least two distinct resistance states

Abstract: In a memory (10), a sensing system (14) detects bit states using one data (54) and two reference (64, 75) inputs, to sense a difference in conductance of a selected memory bit cell (77) and a midpoint reference conductance. Reference conductance is generated as the average conductance of a memory cell (78) in the high conductance state and a memory cell (79) in the low conductance state. The data input (54) is coupled to the selected memory bit cell (77). The two reference inputs are respectively coupled to memory cells in high and low conductance memory states. The sense amplifiers use either current biasing or voltage biasing to apply a sensing voltage within a predetermined voltage range across the bit cells. Capacitance coupled to complementary outputs of the sense amplifiers is balanced by the circuit designs. In one form, the two reference inputs are internally connected. One of several gain stages (90, 150, 110, 130) amplifies the sense amplifier output without injecting parasitic errors.

Stress Memorization Technique (SMT) Optimization for 45nm CMOS

Abstract: In this paper, we present an optimization path of stress memorization technique (SMT) for 45nm node and below using a nitride capping layer. We demonstrate that the understanding of coupling between nitride properties, dopant activation and poly-silicon gate mechanical stress allows enhancing nMOS performance by 7% without pMOS degradation. In contrast to previously reported works on SMT (Chen et al., 2004) - (Singh et al., 2005), a low-cost process compatible with consumer electronics requirements has been successfully developed

Receiver buffer requirement for video streaming over TCP

Abstract: TCP is one of the most widely used transport protocols for video streaming. However, the rate variability of TCP makes it difficult to provide good video quality. To accommodate the variability, video streaming applications require receiver-side buffering. In current practice, however, there are no systematic guidelines for the provisioning of the receiver buffer, and smooth playout is insured through over-provisioning. In this work, we are interested in memory-constrained applications where it is important to determine the right size of receiver buffer in order to insure a prescribed video quality. To that end, we characterize video streaming over TCP in a systematic and quantitative manner. We first model a video streaming system analytically and derive an expression of receiver buffer requirement based on the model. Our analysis shows that the receiver buffer requirement is determined by the network characteristics and desired video quality. Experimental results validate our model and demonstrate that the receiver buffer requirement achieves desired video quality.

Oblique deposition to induce magnetic anisotropy for MRAM cells

Abstract: A method of fabricating a magnetoresistive tunneling junction cell comprising the steps of providing a substrate with a surface, depositing a first magnetic region (17) having a resultant magnetic moment vector onto the substrate, depositing an electrically insulating material (16) onto the first magnetic region, and depositing a second magnetic region (15) onto the electrically insulating material, wherein at least a portion of one of the first and second magnetic regions is formed by depositing said region at a nonzero deposition angle relative to a direction perpendicular to the surface of the substrate to create an induced anisotropy.