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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Patent
19 Mar 1997
TL;DR: In this paper, a sensor (10) includes a cavity (31) formed by a substrate (11), an adhesive (21), and a filter (22), while electrical contacts (17, 18) coupled to the sensing element (14) are located outside the cavity.
Abstract: A sensor (10) includes a cavity (31) formed by a substrate (11), an adhesive (21), and a filter (22). A sensing element (14) is located inside the cavity (31) while electrical contacts (17, 18) coupled to the sensing element (14) are located outside the cavity (31). The filter (22) protects the sensing element (14) from physical damage and contamination during die singulation and other assembly processes. The filter (22) also improves the chemical sensitivity, selectivity, response times, and refresh times of the sensing element (14).

38 citations

Patent
13 Mar 1998
TL;DR: In this paper, a method of manufacturing a semiconductor component with a multi-level interconnect system is described, which includes providing a substrate (11), fabricating a device (12), forming an interconnect layer (15), depositing a dielectric layer (20), and etching a via (31) in the separate interconnect layers.
Abstract: A method of manufacturing a semiconductor component with a multi-level interconnect system includes providing a substrate (11), fabricating a device (12) in the substrate (11), forming an interconnect layer (15) over the substrate (11), depositing a dielectric layer (20) over the interconnect layer (15), depositing a separate interconnect layer (21) over the dielectric layer (20), etching a via (31) in the separate interconnect layer (21) and in the dielectric layer (20), and depositing a different interconnect layer (40) over the separate interconnect layer (21) and in the via (31) wherein the another interconnect layer (40) electrically couples the interconnect layer (15) and the separate interconnect layer (21).

38 citations

Patent
11 Sep 1996
TL;DR: In this paper, a dielectric paste is used in the fabrication of multilayered ceramic modules to create circuit elements, which is a multiphase material in which at least one phase is an alkaline earth metal, transition metal silicate.
Abstract: A dielectric paste material may be used in the fabrication of multilayered ceramic modules to create circuit elements. The dielectric paste is a multiphase material in which at least one phase is an alkaline earth metal, transition metal silicate. This yields a dielectric paste with extremely good K & Q values suitable for high frequency applications which significantly reduce manufacturing costs of modules.

38 citations

Proceedings ArticleDOI
11 Sep 2006
TL;DR: An intelligent evolutionary model composed of a modular morphological neural network (MMNN) trained via an improved genetic algorithm having optimal genetic operators to accelerate convergence of the genetic algorithm is presented.
Abstract: This paper presents an evolutionary morphological approach for designing translation invariant operators for time series forecasting. It consists of an intelligent evolutionary model composed of a modular morphological neural network (MMNN) trained via an improved genetic algorithm (IGA) having optimal genetic operators to accelerate convergence of the genetic algorithm. The proposed design strategy searches for the minimum number of time lags to represent the time series, as well as the weights, architecture and number of modules of the MMNN. An experimental analysis is conducted with the proposed method using six real world financial time series and five well-known performance measurements, demonstrating good performance of MMNN systems for financial time series forecasting.

38 citations

Patent
01 Jun 1992
TL;DR: In this article, a tuning circuit with an integrator with an RC time constant which is proportional to the RC time constants of the analog filter is presented. But the integrator does not provide an output control signal.
Abstract: A tuning circuit (10) and method of operation for tuning an analog filter (40). The tuning circuit (10) has an integrator with an input portion (12) and a comparator portion (14), a counter (32), and a decoder (34). The integrator is implemented with an RC time constant which is proportional to an RC time constant of the analog filter (40). The comparator portion (14) provides an enable signal during the RC time constant of the integrator to the counter (16) which quantizes the RC time constant relative to a clock period of the counter (16). A predetermined decoding is performed to provide an output control signal to control adjustment of the RC time constant of the analog filter (40).

38 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267