Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

High resolution pulse width modulator

Abstract: A pulse width modulator ( 100 ) and method that facilitates high resolution pulse width modulation is provided. The pulse width modulator ( 100 ) creates a pulse width modulated signal having a duty cycle that is proportional to a controllable delay in the modulator. The pulse width modulator combines a first digitally controllable delay ( 102 ) with a delay adjustment ( 104 ) to provide the controllable delay. In one embodiment, a digital counter ( 202 ) is used to provide coarse delay, with the delay adjustment device ( 210 ) coupled to the digital counter ( 202 ) to provide the fine, high resolution, delay control. Together the digital counter ( 202 ) and delay adjustment device ( 210 ) provide high resolution pulse width modulation. In one particular implementation, the analog delay adjustment device ( 100 ) comprises a delay block ( 500 ) designed to provide delay adjustment that is selectively controllable by changing a capacitance in the device.

Stray magnetic shielding for a non-volatile MRAM

Abstract: A non-volatile magneto-resistive memory positioned on a semiconductor substrate is shielded from stray magnetic fields by a passivation layer partially or completely surrounding the non-volatile magneto-resistive memory. The passivation layer includes non-conductive ferrite materials, such as Mn--Zn-Ferrite, Ni--Zn-Ferrite, MnFeO, CuFeO, FeO, or NiFeO, for shielding the non-volatile magneto-resistive memory from stray magnetic fields. The non-conductive ferrite materials may also be in the form of a layer which focuses internally generated magnetic fields on the non-volatile magneto-resistive memory to reduce power requirements.

Method and apparatus for performing wafer level testing of integrated circuit dice

Abstract: A semiconductor wafer (20) having integrated circuit dice (22), wafer conductors (42-47, 50-53), and wafer contact pads (38) formed thereon. The wafer conductors (42-47, 50-53) are used to transfer electrical signals to and from the integrated circuit dice (22) on semiconductor wafer (20) so that wafer level testing and burn-in can be performed on the integrated circuit dice (22). In accordance with one embodiment of the present, each wafer conductor (45, 52) is electrically coupled to the same bonding pad (78) on each integrated circuit dice (22). Each wafer conductor (42-47, 50-53) includes at least a portion of conductor (42-47) which overlies the upper surface of at least one integrated circuit dice (22).

Method for sharing bandwidth using reduced duty cycle signals and media access control

Abstract: A method is provided for transmitting data A first device generates a first signal having a first duty cycle, comprising a first gated-on portion and a first gated-off portion in a time slot; and a second device generates a second signal having second duty cycle, comprising a second gated-on portion and a second gated-off portion in the same time slot The first gated-on portion is generated during a first segment of the time slot and the first gated-off portion is generated during a second segment of the time slot, while the second gated-on portion is generated during the second segment and the second gated-off portion is generated during the first segment Media access control (MAC) can be used to further define positions within time slots and provide error correction, power control, and the like A preamble can be transmitted at an increased power level to facilitate acquisition

Power control feedback loop for adjusting a magnitude of an output signal

Abstract: A circuit for adjusting a magnitude of a transmit signal includes a transmitter (105), providing a transmit signal (107). It also includes a transmitter amplifier (109), receiving the transmit signal (107) and a power control adjustment signal (121), and responsive thereto, providing an amplified transmit signal (111). The circuit also includes a detector (123), for detecting an amplitude of the amplified transmit signal (111). Also included is an error component (137) for determining the difference between the amplitude and a reference level (129). Further provided is a digital signal generator (155), receiving the difference (145), and responsive thereto, generating (157) a reference signal (125) and the power control adjustment signal (117, 121), where the reference level (129) is responsive to the reference signal (125).