Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Thermal modeling and design of 3D integrated circuits

Abstract: 3D interconnect technology has attracted significant interest in the recent past as a means for enabling faster and more efficient integrated circuits (ICs). 3D integration relies on through-silicon vias (TSVs) and bonding of multiple active layers. While this approach provides several electrical benefits, it also offers significant challenges in thermal management. While some work has been done in the past in this field, a comprehensive treatment is still lacking. In the current work, analytical and finite-element models of heat transfer in 3D electronic circuits are developed. The models are used to investigate the limits of thermal feasibility of 3D electronics and to determine the improvements required in traditional packaging in order to accommodate 3D ICs. An analytical model for temperature distribution in a multi-die stack with multiple heat sources is developed. The analytical model is used to extend the traditional concept of thermal resistance in an IC to thermal resistance and thermal sensitivity matrices for a 3D IC. The impact of various geometric parameters and thermophysical properties on thermal performance of a 3D IC is investigated. It is shown that package thermal resistances play a more important role in determining temperature rise compared to thermal resistances intrinsic to the 3D technology, including thermal resistance of bonding layers and TSVs. As a result, an improved bonding layer or TSV thermal resistance does not offer much thermal benefit. An increase in thermal resistance of a 3D IC is predicted as compared to an equivalent System-on-Chip (SoC). This increase is found to be mainly due to the reduced chip footprint. The amount of improvement required in package and heat sink thermal resistances for a logic-on-memory 3D implementation to be thermally feasible is quantified. The results presented in this paper are expected to aid in the development of thermal design guidelines for 3D ICs.

Issues related to the implementation of Pb-free electronic solders in consumer electronics

Abstract: Consumer electronic applications are the primary target of the Pb-free initiative and package assembly and performance is affected by the move from eutectic Sn-Pb to Pb-free solder alloys. This paper outlines the key issues and mitigation possibilities for package assembly using Pb-free solders: High temperature reflow, Interfacial reactions, and Reliability. At the high temperatures required to reflow Pb-free alloys, moisture absorbed into the package can result in delamination and failure. The reaction of the Pb-free solder with Ni and Cu metallizations results in interfacial intermetallics that are not significantly thicker than with Sn-Pb but provide a path for fracture under mechanical loading due to the increased strength of the Pb-free alloys. The reliability issues discussed include thermomechanical fatigue, mechanical shock, electromigration and whiskering. The Pb-free alloys tend to improve thermomechanical fatigue and electromigration performance but are detrimental to mechanical shock and whiskering. Design trade-offs must be made to successfully implement Pb-free alloys into consumer applications.

Method of forming a silicon nitride layer

Abstract: A method of forming a silicon nitride layer or film on a semiconductor wafer structure includes forming a silicon nitride layer on the surface of a wafer structure using a molecular beam of high purity elemental Si and an atomic beam of high purity nitrogen. In a preferred embodiment, a III-V compound semiconductor wafer structure is heated in an ultra high vacuum system to a temperature below the decomposition temperature of said compound semiconductor wafer structure and a silicon nitride layer is formed using a molecular beam of Si provided by either thermal evaporation or electron beam evaporation, and an atomic nitrogen beam provided by either RF or microwave plasma discharge.

Method and circuitry for controlling supply voltage in a data processing system

Abstract: Supply voltages within a data processing system may be controlled by a voltage control module which can provide digital signals to a power management unit to cause changes in supply voltages without software intervention. For example, in one embodiment, a voltage control signal and a standby signal may be provided to control the supply voltages output by a voltage regulator within the power management unit. In one embodiment having multiple processors, a voltage control signal and a standby signal corresponding to each processor may be provided to the power management unit which has a voltage regulator supplying an independently controlled supply voltage to each processor. Alternatively, a voltage regulator, a voltage control signal, and a standby signal may be shared by multiple processors, where the voltage control module may ensure that the supply voltage is changed only when the change is appropriate for all processors sharing the same voltage regulator.

High performance 32nm SOI CMOS with high-k/metal gate and 0.149µm 2 SRAM and ultra low-k back end with eleven levels of copper

Abstract: This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 µm2. V min operation down to 0.6 V in a 16Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by hig-hk/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress liner (DSL). Gate lengths down to 25 nm have been demonstrated enabling performance without the power penalty from gate capacitance. AC drive currents of 1.55 mA/um and 1.22 mA/um have been achieved at an off-state of 100 nA/µm and V DD of 1 V for NFET and PFET, respectively. For the first time, we have also demonstrated that SOI maintains performance benefit over bulk silicon in high-k/metal gate and 32 nm ground rules.