Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Methods and apparatus for simulating distributed effects

Abstract: In general, various embodiments of the present invention relate to systems and methods for simulating distributed effects by providing a meshing pattern (200) (e.g., a two-dimensional meshing pattern that is part of a recognition layer), applying that meshing pattern to the physical layout (100), and partitioning the physical layout into a three-dimensional netlist (300) of components derived from the unit cells defined by the meshing pattern (200), thereby modeling the parasitics within the design.

Metal gate transistor for cmos process and method for making

Abstract: A method for forming a semiconductor device (100) includes a semiconductor substrate having a first region (104), forming a gate dielectric (108) over the first region, forming a conductive metal oxide (110) over the gate dielectric, forming an oxidation resistant barrier layer (111) over the conductive metal oxide, and forming a capping layer (116) over the oxidation resistant barrier layer. In one embodiment, the conductive metal oxide is IrO2, MoO2, and RuO2, and the oxidation resistant barrier layer includes TiN.

Method and apparatus for updating carrier channel allocations

Abstract: In a communication system that utilizes DMT technology to couple a primary site (102) to a plurality of secondary sites (104-108), carrier channel allocations may be updated as follows. At periodic intervals, the primary site requests updating bit loading information from the secondary sites. Upon receiving the updated bit loading information, the primary site (102) determines an updated call bit loading table for each active call. From this, the primary site (102) determines whether current carrier channel allocation provides sufficient bandwidth. When the current carrier channel allocation does not provide the sufficient bandwidth, the primary site modifies the current carrier channel allocation to meet the bandwidth requirements.

Impact of Technology Scaling on SRAM Soft Error Rates

Abstract: Soft error rates for triple-well and dual-well SRAM circuits over the past few technology generations have shown an apparently inconsistent behavior. This work compares the heavy-ion induced upset cross-section in 28, 40, and 65 nm dual- and triple-well SRAMs over a wide range of particle LETs. Similar experiments on identical layouts for all these technologies along with 3-D TCAD simulations are used to identify the dominant mechanisms for single-event upsets. Results demonstrate that the well-engineering strongly influence the single-event response of SRAMs. Layout also plays an important role and the combined effects of well-engineering and layout determine the soft-error sensitivity of SRAMs fabricated in advanced technology nodes.

A 90-nm CMOS 5-GHz Ring-Oscillator PLL With Delay-Discriminator-Based Active Phase-Noise Cancellation

Abstract: Ring oscillators (ROs) provide a low-cost digital VCO solution in fully integrated PLLs. However, due to their supply noise sensitivity and high noise floor, their applications have been limited to low-performance applications. The proposed architecture introduces an analog feed-forward adaptive phase-noise cancellation architecture that extracts and suppresses phase noise of ROs outside the PLL bandwidth. The proposed technique can improve the phase noise at an arbitrary offset frequency and bandwidth, and, after initial calibration for gain, it is insensitive to process, voltage, and temperature variations. An experimental fractional PLL, with a loop bandwidth of 200 kHz, is utilized to demonstrate the active phase-noise cancellation approach. The cancellation loop is designed to suppress the phase noise at 1-MHz offset by 12.5 dB and reference spur by 13 dB with less than 17% increase in the overall power consumption at 5.1-GHz frequency. The measured phase noise at 1-MHz offset after cancellation is ${-}$ 105 dBc/Hz. The proposed RO-PLL is fabricated in 90-nm CMOS process. With noise cancellation loop enabled, the PLL consumes 24.7 mA at 1.2-V supply.