Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Semiconductor device structure and method for forming

Abstract: A semiconductor device structure has trenches of two widths or more The smallest widths are to maximize density The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels

Progressive memory initialization with waitpoints

Abstract: A method includes initializing a counter value of a hardware counter. The method further includes iteratively adjusting the counter value and storing an initialization value to a memory location using a memory address based on the counter value. The method also includes generating an interrupt request based on a comparison of the counter value to a waitpoint value concurrent with iteratively adjusting and storing. A memory device includes a memory array and an initialization module. The initialization module includes a counter, a register to store a waitpoint value, write logic configured to write an initialization value to a memory location of the memory array associated with a memory address that is based on a counter value of the counter, and interrupt logic configured to generate an interrupt request based on a comparison of the counter value of the counter to the waitpoint value.

Method and system for dynamic aggregation in a wireless network

Abstract: A method is provided for dynamically controlling aggregation in an ultrawide bandwidth wireless device. In this method, a device receives a plurality of intermediate service data units at an intermediate layer, aggregates at least two of the plurality off intermediate service data units to form an intermediate protocol data unit, and sends the intermediate protocol data unit to a physical layer. The physical layer generates a data frame based on the intermediate protocol data unit and information corresponding to the physical layer, and transmits the data frame in a data stream. The device selects an intermediate size criteria for the intermediate protocol data unit based on a desired frame size criteria for the data frame. The aggregating of the at least two of the plurality of intermediate layer service data units is performed such that an actual intermediate layer protocol data unit size corresponds to the intermediate size criteria.

Method and apparatus for secure scan testing

Abstract: A processor, scan controller, and method for protecting sensitive information from electronic hacking is disclosed. To maintain the security of the sensitive data present in a processor, the scan controller denies access to the scan chain until data is cleared from scan-observable portions of the processor, then clears the scan chain again prior to exiting test mode and resuming normal operation. Clearing or otherwise modifying data stored in the scan-observable portions of a processor when transitioning to and/or from a test mode will prevent unauthorized personnel from simply shifting secure data out of the scan chain, and from pre-loading data into the scan chain prior to normal operation in an attempt to set sensitive state information.

Vertically integrated sensor structure and method

Abstract: A vertically integrated sensor structure (60) includes a base substrate (71) and a cap substrate (72) bonded to the base substrate (71). The base substrate (71) includes a transducer (78) for sensing an environmental condition. The cap substrate (72) includes electronic devices (92) formed on one surface to process output signals from the transducer (78). The sensor structure (60) provides an integrated structure that isolates sensitive components from harsh environments.