Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Method and apparatus for performing operative testing on an integrated circuit

Abstract: A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built in the corners of the die (5) and connected to the monitor unit (10) via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch (20) in the monitor unit (10). Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system. Other embodiments provide the monitor unit on the die, allowing for later testing and user confirmation.

Semiconductor device having built-in high frequency bypass capacitor

Abstract: A high frequency bypass capacitor (36, 36') is built into a thin-film portion (16, 16') of a polymer carrier substrate (15) of a PBGA (10). The carrier substrate (15) has both a stiffener (18) and a thin-film portion (16, 16') which has multiple metal layers (24, 28, 30, 32). The power supply planes (28, 30) of these metal layers are used to form built-in bypass capacitors (36, 36'), wherein the power supply planes are specifically designed to be adjacent and parallel layers. An ultra thin film laminate construction provides thin dielectric films (26) between the metal layers to allow the bypass capacitor to be placed very dose to the attached semiconductor die (12) to further reduce parasitic inductance and resistance between die connections (14) and the bypass capacitor. The built-in feature minimizes inherent parasitic series inductance and resistance, thus enabling the filtering of unwanted low pulse width glitches on a power plane connected to VLSI devices at operating frequencies at or above 100 MHz.

Ultra-thin die and method of fabricating same

Abstract: In accordance with a specific embodiment, a method of processing a semiconductor substrate is disclosed whereby the substrate is thinned, and the dice formed on the substrate are singulated by a common process. Trench regions are formed on a backside of the substrate. An isotropic etch of the backside results in a thinning of the substrate while maintaining the depth of the trenches, thereby facilitating singulation of the die.

A New Control Approach Based on the Differential Flatness Theory for an AC/DC Converter Used in Electric Vehicles

Abstract: AC/DC converters used for charging high-voltage battery banks in electric vehicles from the utility mains, generally, consist of two stages. The first is a power factor correction (PFC) ac/dc boost converter to reduce the input current harmonics injected to the utility grid and convert input ac voltage to an intermediate dc voltage (dc-bus voltage). The second part is an isolated dc/dc converter for providing high-frequency galvanic isolation. This paper presents a novel intelligent control law based on the differential flatness theory to control the input power of the PFC stage which is determined by the charging characteristics of the high-energy battery bank, instead of controlling the intermediate dc-bus voltage at a constant value as done in the conventional controller. Application of the proposed control law to such an ac/dc converter helps improve the dynamic behavior of the input PFC stage compared to the conventional controller and also achieve load adaptive regulation of the intermediate dc-bus voltage. Such load-adaptive dc-bus voltage regulation allows the dc/dc full-bridge converter to operate optimally from no-load to full-load conditions unlike the conventional controller with constant dc-bus voltage which forces the dc/dc full-bridge to operate with very low duty ratios at no-load conditions. Experimental results from a 3-kW ac/dc converter are presented in the paper to validate the proposed control method. The improved converter performance and increased efficiency as compared to the conventional control method proves the superiority of the proposed technique.

Method and apparatus for demodulation and power control bit detection in a spread spectrum communication system

Abstract: A receiver circuit (400, 500) receives a spread spectrum communication signal, such as a DS-CDMA signal, including a pilot channel and including a power control designator. The signal is despread and decoded. The pilot symbols on the pilot channel are provided to a channel estimator (408) for estimating the channel phase and channel gain of the communication channel. This estimate is provided to a demodulator (422) for demodulating the traffic channel symbols. The pilot symbols are provided to another channel estimator (410) for estimating channel phase and channel gain for the power control designator. This estimate is provided to a demodulator (424) for demodulating the power control designator. The traffic channel symbols are delayed a predetermined time in a delay element (420) before demodulating. The power control designator is delayed a short time or not at all in a short delay element (418) before demodulation.