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Institution

Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..


Papers
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Journal ArticleDOI
TL;DR: In this paper, the first demonstration of a magnetoresistive random access memory (MRAM) circuit incorporating MgO-based magnetic tunnel junction (MTJ) material for higher performance was reported.
Abstract: We report the first demonstration of a magnetoresistive random access memory (MRAM) circuit incorporating MgO-based magnetic tunnel junction (MTJ) material for higher performance. We compare our results to those of AlOx-based devices, and we discuss the MTJ process optimization and material changes that made the demonstration possible.We present data on key MTJ material attributes for different oxidation processes and free-layer alloys, including resistance distributions, bias dependence, free-layer magnetic properties, interlayer coupling, breakdown voltage, and thermal endurance. A tunneling magnetoresistance (TMR) greater than 230% was achieved with CoFeB free layers and greater than 85% with NiFe free layers. Although the TMR with NiFe is at the low end of our MgO comparison, even this MTJ material enables faster access times, since its TMR is almost double that of a similar structure with an AlOx barrier. Bit-to-bit resistance distributions are somewhat wider for MgO barriers, with sigma about 1.5% compared to about 0.9% for AlOx. The read access time of our 4 Mb toggle MRAM circuit was reduced from 21 ns with AlOx to a circuit-limited 17 ns with MgO.

91 citations

Patent
07 Oct 1996
TL;DR: In this article, a method of fabricating GMR devices on a CMOS substrate structure with a semiconductor device formed therein is described, which includes forming a dielectric system with a planar surface having a roughness in a range of 1 Å to 20 RMS on the substrate.
Abstract: A method of fabricating GMR devices on a CMOS substrate structure with a semiconductor device formed therein. The method includes forming a dielectric system with a planar surface having a roughness in a range of 1 Å to 20 Å RMS on the substrate; disposing and patterning films of giant magneto-resistive material on the planar surface so as to form a memory cell; disposing a dielectric cap on the cell so as to seal the cell and provide a barrier to subsequent operations; forming vias through the dielectric cap and the dielectric system to interconnects of the semiconductor device; forming vias through the dielectric cap to the magnetic memory cell; and depositing a metal system through the vias to the interconnects and to the memory cell.

91 citations

Patent
06 Apr 2004
TL;DR: In this article, power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current.
Abstract: Power consumption may be reduced through the use of power gating in which power is removed from circuit blocks or portions of circuit blocks in order to reduce leakage current. One embodiment uses a modified state retention flip-flop capable of retaining state when power is removed or partially removed from the circuit. Another embodiment uses a modified state retention buffer capable of retaining state when power is removed or partially removed from the circuit. The state retention flip-flop and buffer may be used to allow for state retention while still reducing leakage current. Also disclosed are various methods of reducing power and retaining state using, for example, the state retention flip-flops and buffers. For example, software, hardware, or a combination of software and hardware methods may be used to enter a deep sleep or idle mode while retaining state.

90 citations

Patent
28 Aug 2006
TL;DR: In this paper, a spin torque MRAM cell with a reduced switching current was proposed, where standard materials may be used for a free layer and alternating synthetic antiferromagnetic layers for a keeper layer.
Abstract: A magnetic random access memory device include a spin torque MRAM cell ( 100 ) having a reduced switching current (I c ) wherein standard materials may be used for a free layer ( 108 ). A fixed magnetic element ( 112 ) polarizes electrons passing therethrough, and the free magnetic element ( 108 ) having a first plane anisotropy comprises a first magnetization ( 130 ) whose direction is varied by the spin torque of the polarized electrons. An insulator ( 110 ) is positioned between the fixed magnetic element ( 112 ) and the free magnetic element ( 108 ), and a keeper layer ( 104 ) positioned contiguous to the free magnetic element ( 108 ) and having a second plane anisotropy orthogonal to the first plane anisotropy, reduces the first plane anisotropy and hence reduces the spin torque switching current (I c ). The keeper layer ( 104 ) may include alternating synthetic antiferromagnetic layers ( 132, 134 ) of magnetization approximately equal in magnitude and opposite in direction.

90 citations

Journal ArticleDOI
TL;DR: The parallel neuromorphic processor architectures for spiking neural networks on FPGA address several critical issues pertaining to efficient parallelization of the update of membrane potentials, on-chip storage of synaptic weights and integration of approximate arithmetic units.

88 citations


Authors

Showing all 7673 results

NameH-indexPapersCitations
David Blaauw8775029855
Krishnendu Chakrabarty7999627583
Rajesh Gupta7893624158
Philippe Renaud7777326868
Min Zhao7154724549
Gary L. Miller6330613010
Paul S. Ho6047513444
Ravi Subrahmanyan5935314244
Jing Shi5322210098
A. Alec Talin5231112981
Chi Hou Chan485119504
Lin Shao4838012737
Johan Åkerman483069814
Philip J. Tobin471866502
Alexander A. Demkov473317926
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Performance
Metrics
No. of papers from the Institution in previous years
YearPapers
20211
20203
201910
201826
201779
2016267