Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Apparatus and method for power management in a tire pressure monitoring system

Abstract: A system (10) and method manages battery (13) power in a wheel module (11) for indicating when air pressure in a tire falls below a recommended value. Tire air pressure is sensed with a pressure sensor (16). Tire air temperature is sensed with a temperature sensor (18). A determination is made whether the air pressure is increasing or decreasing with respect to time. Based upon whether a ratio of the air pressure and the air temperature is increasing, decreasing or remaining constant with respect to time, tire motion is inferred without directly sensing acceleration or movement of the tire. Power management circuitry (14) controls battery power to enable sensing of air pressure and air temperature at measurement intervals that are longer in time when the tire is not in motion.

Method of forming nanocrystals in a memory device

Abstract: Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

High-permittivity dielectric capacitor for use in a semiconductor device and process for making the same

Abstract: A high-permittivity dielectric capacitor (28) having a refractory-metal oxide layer (16) framing the first electrode (14) of the capacitor (28) and separating a high-permittivity dielectric layer (24) from an insulating layer (12) underlying the capacitor (28). The high-permittivity dielectric layer (16) makes contact with the first electrode (14) through an opening (18) in the refractory-metal oxide layer (16). The refractory-metal oxide layer (16) separates the high-permittivity dielectric layer (24) from the insulating layer (12) in all regions away from the opening (18) in the refractory-metal oxide layer (16). During fabrication of the capacitor (28), when the high-permittivity dielectric layer (24) is patterned, the refractory-metal oxide layer (16) provides an etch-stop.

Process for forming an intermetallic layer

Abstract: The present invention includes a process for forming an intermetallic layer and a device formed by the process. The process includes a reaction step where a metal-containing layer reacts with a metal-containing gas, wherein the metals of the layer and gas are different. In one embodiment of the present invention, titanium aluminide may be formed on the sides of an interconnect. The process may be performed in a variety of equipment, such as a furnace, a rapid thermal processor, a plasma etcher, and a sputter deposition machine. The reaction to form the intermetallic layer is typically performed while the substrate is at a temperature no more than 700 degrees Celsius.

FinFET Formation with a Thermal Oxide Spacer Hard Mask Formed from Crystalline Silicon Layer

Abstract: A semiconductor process and apparatus provide a FinFET device by forming a second single crystal semiconductor layer ( 19 ) that is isolated from an underlying first single crystal semiconductor layer ( 17 ) by a buried insulator layer ( 18 ); patterning and etching the second single crystal semiconductor layer ( 19 ) to form a single crystal mandrel ( 42 ) having vertical sidewalls; thermally oxidizing the vertical sidewalls of the single crystal mandrel to grow oxide spacers ( 52 ) having a substantially uniform thickness; selectively removing any remaining portion of the single crystal mandrel ( 42 ) while substantially retaining the oxide spacers ( 52 ); and selectively etching the first single crystal semiconductor layer ( 17 ) using the oxide spacers ( 52 ) to form one or more FinFET channel regions ( 92 ).