Freescale Semiconductor

About: Freescale Semiconductor is a based out in . It is known for research contribution in the topics: Layer (electronics) & Signal. The organization has 7673 authors who have published 10781 publications receiving 149123 citations. The organization is also known as: Freescale Semiconductor, Inc..

Direct memory access controller and method therefor

Abstract: Direct memory access controller (DMAC) (54) adapted to directly execute C language style FOR tasks assigned by a processor (70), where the FOR task includes a movement of a data element from a first location to a second location in memory The DMAC includes multiple execution units (EUs) (88, 90, 92), each to perform an arithmetic or logical operation, and a FOR task controller (80, 82, 86) to perform the data movement The FOR task controller selects the operation to be performed by the EU In one embodiment, the FOR task is made up of C language type FOR loops, where descriptors identify the control and body of the loop The descriptors identify the source of operands for an EU, and the source may be changed within a FOR task A descriptor specifies a function code for an EU and may specify multiple sets of operands for the EU

Generalized reference signaling scheme for mu-mimo using arbitrarily precoded reference signals

Abstract: A multi-user MIMO downlink beamforming system (200) is provided to enable transmit beamforming vectors to be efficiently provided to a subset of user equipment devices (201.i), where spatial separation or zero-forcing transmit beamformers (wi) are computed at the base station (210) and used to generate precoded reference signals (216). The precoded reference signals (216) are fed forward to the user equipment devices (201.i) which apply one or more hypothesis tests (207.i, 208.i) to the precoded reference signals to extract the precoding matrix (W), including the specific transmit beamforming vector (wUE) designed for the user equipment, and this extracted information is used to generate receive beamformers (vi).

Microprocessor having a content addressable memory (CAM) device as a functional unit therein and method of operation

Abstract: A microprocessor architecture (310) has a plurality of functional units arranged in a parallel manner between one or more source buses (412 and/or 414) and one or more result buses (490). At least one of the functional units within the architecture is a content addressable memory (CAM) functional unit (430) which can be issued CPU instructions via a sequencer (480) much like any other functional unit. The operation of the CAM (430) may be pipelined in one or more stages so that the CAM's throughput may be increased to accommodate the higher clock rates that are likely used within the architecture (310). One embodiment involves pipelining the CAM operation in three stages (510, 520, and 530) in order to sequentially perform data input and precharge operations, followed by match operations, and followed Finally by priority encoding and data output.

Method of making a transfer molded semiconductor device

Abstract: A method of making a pad array chip carrier package is disclosed. A semiconductor device (10) is bonded to a ceramic substrate (12). The semiconductor device may be attached to the substrate by wirebonding, tab bonding or flip chip bonding. The bonded assembly (16) is then attached to a flexible temporary support substrate (18) by means of an adhesive (19). The entire assembly is then placed into a mold cavity (20 and 22) and registered against the temporary support substrate (18). Plastic material (30) is molded about the semiconductor device and associated wirebonds in order to encapsulate the device. After removal from the mold, the encapsulated assembly is removed from the temporary support substrate (18) by peeling the temporary support substrate (18) from the circuit substrate.

Graded-channel semiconductor device

Abstract: A graded-channel semiconductor device (10) includes a substrate region (11) having a major surface (12). A source region (13) and a drain region (14) are formed in the substrate region (11) and are spaced apart to form a channel region (16). A doped region (18) is formed in the channel region (16) and is spaced apart from the source region (13), the drain region (14), and the major surface (12). The doped region (18) has the same conductivity type as the channel region (16), but has a higher dopant concentration. The device (10) exhibits an enhanced punch-through resistance and improved performance compared to prior art short channel structures.